eZ80L92 MCU
Product Specification
62
Signal timing for Intel® Bus Mode with multiplexed address and data is illustrated for a
Read operation in Figure 12 and for a Write operation in Figure 13. In the figures, each
Intel® Bus Mode state is 2 eZ80 system clock cycles in duration. Figure 12 and Figure 13
also illustrate the assertion of one WAIT state (TWAIT) by the selected peripheral.
T
WAIT
T1
T2
T3
T4
System Clock
ADDR[23:0]
DATA[7:0]
CSx
ALE
RD
READY
WR
MREQ
or IORQ
®
Figure 12. Intel Bus Mode Read Timing Example (Multiplexed Address and Data Bus)
PS013015-0316
Chip Selects and Wait States
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