eZ80L92 MCU
Product Specification
11
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol
Function
Power Supply
Ground
Signal Direction
Description
Power Supply.
Ground.
43
44
45
V
V
DD
SS
IORQ
MREQ
RD
Input/Output
Request
Bidirectional, Active IORQ indicates that the CPU is accessing
Low
a location in I/O space. RD and WR
indicate the type of access. The eZ80L92
MCU does not drive this line during
RESET. It is an input in bus acknowledge
cycles.
46
47
Memory
Request
Bidirectional, Active MREQ Low indicates that the CPU is
Low
accessing a location in memory. The RD,
WR, and INSTRD signals indicate the
type of access. The eZ80L92 MCU does
not drive this line during RESET. It is an
input in bus acknowledge cycles.
Read
Write
Output, Active Low
RD Low indicates that the eZ80L92 MCU
is reading from the current address
location. This pin is tristated during bus
acknowledge cycles.
48
49
WR
Output, Active Low
Output, Active Low
WR indicates that the CPU is writing to the
current address location. This pin is
tristated during bus acknowledge cycles.
INSTRD
Instruction
Read Indicator
INSTRD (with MREQ and RD) indicates
the eZ80L92 MCU is fetching an
instruction from memory. This pin is
tristated during bus acknowledge cycles.
50
51
WAIT
WAIT Request Input, Active Low
Driving the WAIT pin Low forces the CPU
to wait additional clock cycles for an
external peripheral or external memory to
complete its Read or Write operation.
RESET
Reset
Schmitt Trigger Input, This signal is used to initialize the
Active Low
eZ80L92 MCU. This input must be Low for
a minimum of 3 system clock cycles, and
must be held Low until the clock is stable.
This input includes a Schmitt trigger to
allow RC rise times.
PS013014-0107
Architectural Overview
ZILOG [ ZILOG, INC. ]
