eZ80L92 MCU
Product Specification
12
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol
Function
Signal Direction
Description
52
NMI
Nonmaskable Schmitt Trigger Input, The NMI input is a higher priority input
Interrupt
Active Low
than the maskable interrupts. It is always
recognized at the end of an instruction,
regardless of the state of the interrupt
enable control bits. This input includes a
Schmitt trigger to allow RC rise times.
53
54
BUSREQ
BUSACK
Bus Request Input, Active Low
External devices can request the eZ80L92
MCU to release the memory interface bus
for their use, by driving this pin Low.
Bus
Output, Active Low
The eZ80L92 MCU responds to a Low on
BUSREQ, by tristating the address, data,
and control signals, and by driving the
BUSACK line Low. During bus
Acknowledge
acknowledge cycles ADDR[23:0], IORQ,
and MREQ are inputs.
55
HALT_SLP HALT and
SLEEP
Output, Active Low
A Low on this pin indicates that the CPU
has entered either HALT or SLEEP mode
because of execution of either a HALT or
SLP instruction.
Indicator
56
57
58
V
V
Power Supply
Ground
Power Supply.
Ground.
DD
SS
RTC_XIN
Real-Time
Clock Crystal
Input
Input
This pin is the input to the low-power
32 kHz crystal oscillator for the Real-Time
Clock.
59
RTC_XOUT Real-Time
Clock Crystal
Bidirectional
This pin is the output from the low-power
32 kHz crystal oscillator for the Real-Time
Clock. This pin is an input when the RTC
is configured to operate from 50/60 Hz
input clock signals and the 32 kHz crystal
oscillator is disabled.
Output
60
RTC_V
Real-Time
Clock Power
Supply
Power supply for the Real-Time Clock and
associated 32 kHz oscillator. Isolated from
the power supply to the remainder of the
chip. A battery can be connected to this
pin to supply constant power to the
DD
Real-Time Clock and 32 kHz oscillator.
61
62
V
Ground
Ground.
SS
TMS
JTAG Test
Input
JTAG Mode Select Input.
Mode Select
PS013014-0107
Architectural Overview
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