eZ80L92 MCU
Product Specification
7
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol
Function
Signal Direction
Description
14
15
16
17
ADDR11
ADDR12
ADDR13
ADDR14
Address Bus
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Address Bus
Address Bus
Address Bus
Bidirectional
Bidirectional
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
18
19
20
V
V
Power Supply
Ground
Power Supply.
Ground.
DD
SS
ADDR15
Address Bus
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
PS013014-0107
Architectural Overview
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