eZ80L92 MCU
Product Specification
9
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol
Function
Signal Direction
Description
26
27
28
ADDR21
ADDR22
ADDR23
Address Bus
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Address Bus
Address Bus
Bidirectional
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
29
30
31
32
CS0
CS1
CS2
CS3
Chip Select 0 Output, Active Low
Chip Select 1 Output, Active Low
Chip Select 2 Output, Active Low
Chip Select 3 Output, Active Low
CS0 Low indicates that an access is
occurring in the defined CS0 memory or
I/O address space.
CS1 Low indicates that an access is
occurring in the defined CS1 memory or
I/O address space.
CS2 Low indicates that an access is
occurring in the defined CS2 memory or
I/O address space.
CS3 Low indicates that an access is
occurring in the defined CS3 memory or
I/O address space.
33
34
V
V
Power Supply
Ground
Power Supply.
Ground.
DD
SS
PS013014-0107
Architectural Overview
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