eZ80L92 MCU
Product Specification
180
Bit
Position
Value Description
7
0
1
0
0
1
0
The CPU is not functioning in ZDI mode.
The CPU is currently functioning in ZDI mode.
zdi_active
6
Reserved.
5
ZLP12840 is not currently in HALT or SLEEP mode.
ZLP12840 is currently in HALT or SLEEP mode.
halt_SLP
4
ADL
The CPU is operating in Z80 MEMORY mode.
(ADL bit = 0).
1
The CPU is operating in ADL MEMORY mode.
(ADL bit = 1).
3
0
1
0
The CPU’s Mixed-Memory mode (MADL) bit is reset to 0.
The CPU’s Mixed-Memory mode (MADL) bit is set to 1.
MADL
2
IEF1
The CPU’s Interrupt Enable Flag 1 is reset to 0. Maskable
interrupts are disabled.
1
The CPU’s Interrupt Enable Flag 1 is set to 1. Maskable
interrupts are enabled.
[1:0]
00 Reserved.
Reserved
ZDI Read Registers—Low, High, and Upper
The ZDI register Read-Only address space offers Low, High, and Upper functions, which
contain the value read by a Read operation from the ZDI Read/Write Control register
(ZDI_RW_CTL). This data is valid only while in ZDI BREAK mode and only if the
instruction is read by a request from the ZDI Read/Write Control register. See Table 104.
Table 104. ZDI Read Registers—Low, High and Upper (ZDI_RD_L = 10h,
ZDI_RD_H = 11h, and ZDI_RD_U = 12h in the ZDI Register Read-Only
Address Space)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
CPU Access
Note: R = Read-only.
R
R
R
R
R
R
R
R
PS013015-0316
Zilog Debug Interface
ZILOG [ ZILOG, INC. ]
