eZ80L92 MCU
Product Specification
183
On-Chip Instrumentation
On-Chip Instrumentation1 (OCI™) for the Zilog eZ80 CPU core enables powerful debug-
ging features. The OCI provides run control, memory and register visibility, complex
breakpoints, and trace history features.
The OCI employs all the functions of the Zilog Debug Interface (ZDI) as described in the
ZDI section. It also adds the following debug features:
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Control through a 4-pin JTAG port that conforms to IEEE Standard 1149.1 (Test Ac-
cess Port and Boundary-Scan Architecture)2.
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Complex break-point trigger functions.
Break-point enhancements, such as the ability to:
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Define two break-point addresses that form a range.
Break on masked data values.
Start or stop trace.
Assert a trigger output signal.
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Trace history buffer.
Software break-point instruction.
OCI has the following sections:
1. JTAG interface.
2. ZDI debug control.
3. Trace buffer memory.
4. Complex triggers.
OCI Activation
The OCI features clock initialization circuitry so that external debug hardware can be
detected during power up. The external debugger must drive the OCI clock pin (TCK)
Low at least two system clock cycles prior to the end of the RESET to activate the OCI
block. If TCK is High at the end of the RESET, the OCI block shuts down so that it does
not draw power in normal product operation. When the OCI is shut down, ZDI is enabled
directly and can be accessed through the clock (TCK) and data (TDI) pins. For more infor-
mation on ZDI, see Zilog Debug Interface on page 160.
1. On-Chip Instrumentation and OCI are trademarks of First Silicon Solutions, Inc.
2. The eZ80L92 MCU does not contain the boundary scan register required for 1149.1 compliance.
PS013015-0316
On-Chip Instrumentation
ZILOG [ ZILOG, INC. ]
