ZL50022
Data Sheet
External Read/Write Address: 006CH
Reset Value: 0002H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
0
OJP2
OJP1
OJP0
Bit
Name
Description
15 - 3
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
2 - 0
OJP2 - 0
Output Jitter Performance Bits
These bits are used to control the DPLL output jitter performance with respect to the
noise received through the output pins. The higher value (unsigned) means more
filtering, while zero means filter bypass. The default value of 2H gives the best
performance for most circumstances.
Table 44 - Output Jitter Control Register (OJCR) Bits
External Read/Write Address: 0100H - 011FH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
4
3
2
1
0
0
STIN[n]
BD2
STIN[n]
BD1
STIN[n]
BD0
STIN[n]
SMP1
STIN[n]
SMP0
STIN[n]
DR3
STIN[n]
DR2
STIN[n]
DR1
STIN[n]
DR0
Bit
Name
Description
15 - 9
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
8 - 6
STIN[n]BD2 - 0
Input Stream[n] Bit Delay Bits.
The binary value of these bits refers to the number of bits that the input stream
will be delayed relative to FPi. The maximum value is 7. Zero means no delay.
Input Data Sampling Point Selection Bits
5 - 4
STIN[n]SMP1 - 0
Sampling Point
(2.048 Mbps, 4.096 Mbps, 8.192 Mbps
streams)
Sampling Point
(16.384 Mbps
streams)
STIN[n]SMP1-0
00
01
10
11
3/4 point
1/4 point
2/4 point
4/4 point
2/4 point
4/4 point
Table 45 - Stream Input Control Register 0 - 31 (SICR0 - 31) BIts
79
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
