ZL50022
Data Sheet
DPLL Performance Characteristics† - Accuracy & Switching
Conditions/
Characteristics
Min
Max
Units
Notes‡
1
2
3
4
5
6
7
8
9
Freerun Accuracy
-0.003
-0.03
-260
0
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ns
1,5,7
1,4,8
Initial Holdover Frequency Stability
0.03
260
82.5
64.5
248
242
31
Pull-in/Hold-in Range (Stratum 4E)
1,3,7,9
1,3,7,9,12
Reference Far Hysteresis Limit (Stratum 4E)
Reference Near Hysteresis Limit (Stratum 4E)
Reference Far Hysteresis Limit (Relaxed Stratum 4E)
Reference Near Hysteresis Limit (Relaxed Stratum 4E)
Output phase continuity for reference switch1
Normal output phase alignment speed (phase slope)
-82.5
-64.5
-248
1,3,7,9,13
-242
11
10
56
µs/s
s
10 Normal phase lock time2
75
1,3,7,9,10
1. Reference switching to normal, holdover, or freerun mode
2. -32 to +32 ppm locking
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ See “Performance Characteristics Notes” on page 118.
.
DPLL Performance Characteristics† - Output Jitter Generation (Unfiltered except for CKo5)
Typ.‡
Characteristics
Units
Conditions/Notes*
1
2
3
4
5
Jitter at CKo0 and CKo3 (4.096 MHz)
810
800
710
670
ps-pp
ps-pp
ps-pp
ps-pp
1-6,14
Jitter at CKo1 and CKo3 (8.192 MHz)
Jitter at CKo2 and CKo3 (16.384 MHz)
Jitter at CKo3 (4.096, 8.192, 16.384, or 32.768 MHz)
Jitter at CKo4 (1.544 MHz or 2.048 MHz)
1.544 MHz
2.048 MHz
1060
630
ps-pp
ps-pp
6
Jitter at CKo5 (19.44 MHz)
unfiltered jitter
770
540
460
510
ps-pp
ps-pp
ps-pp
ps-pp
500 Hz - 1.3 MHz jitter
65 kHz - 1.3 MHz jitter
12 kHz - 1.3 MHz jitter
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* See “Performance Characteristics Notes” on page 118
117
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
