ZL38001
Data Sheet
FUNCTIONAL DESCRIPTION FOR USING THE BOOTABLE RAM
BOOTLOAD MODE - Microport Access is to bootload RAM (BRAM)
R/W
W
Address
Data
3fh
Writes "data" to BRC reg.
(= 1 1 1 1 1 1 b)
- Bootload frozen; BRAM contents are NOT affected.
BRC Register
Bits
W
R
other than 3fh
1 x x x x x b
Writes "data" to next byte in BRAM (bootloading.)
C3C2C1C0
Reads back "data" = BRC reg value.
- Bootload frozen; BRAM contents are NOT affected.
X 1 0 0
R
0 x x x x x b
Reads back "data" = SIG reg value.
- Bootload frozen; BRAM contents are NOT affected.
NON-BOOTLOAD MODE - Microport Access is to device registers (DREGs)
BRC Register
Bits
R/W
W
Address
Data
any
Writes "data" to corresponding DREG.
C3C2C1C0
(= a5 a4 a3 a2 a1 a0 b)
R
any
Reads back "data" = corresponding DREG value.
X 0 0 0
(= a5 a4 a3 a2 a1 a0 b)
PROGRAM EXECUTION MODES
C3C2C1C0
0 0 0 0
Execute program in ROM, bootload mode disabled.
- BRAM address counter reset to initial (ready) state.
- SIG reg reseeded to initial (ready) state
C3C2C1C0
0 1 0 0
Execute program in ROM, while bootloading the RAM.
- BRAM address counter increments on microport writes (except to 3fh)
- SIG reg recalculates signature on microport writes (except to 3fh)
C3C2C1C0
1 0 0 0
Execute program in RAM, bootload mode disabled.
- BRAM address counter reset to initial (ready) state.
- SIG reg reseeded to initial (ready) state
C3C2C1C0
1 1 0 0
- NOT RECOMMENDED -
(Execute program in RAM, while bootloading the RAM)
Table 5 - Bootload RAM Control (BRC) Register States
Note: bits C1 C0 are reserved, and must be set to zero.
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
