ZL38001
Data Sheet
Sign-Magnitude
ITU-T (G.711)
FORMAT=1
FORMAT=0
PCM Code
µ/A-LAW
µ-LAW
A-LAW
LAW = 0 or 1
1111 1111
LAW = 0
1000 0000
1111 1111
0111 1111
0000 0000
LAW =1
+ Full Scale
+ Zero
1010 1010
1101 0101
0101 0101
0010 1010
1000 0000
0000 0000
0111 1111
- Zero
- Full Scale
Table 4 - Companded PCM
2.4 Linear PCM
The 16-bit 2’s complement PCM linear coding permits a dynamic range beyond that which is specified in ITU-T
G.711 for companded PCM. The echo-cancellation algorithm will accept 16-bits 2’s complement linear code which
gives a maximum signal level of +15 dBm0.
2.5 Bit Clock (BCLK/C4i)
The BCLK/C4i pin is used to clock the PCM data for GCI and ST-BUS (C4i) interfaces, as well as for the SSI
(BCLK) interface.
In SSI operation, the bit rate is determined by the BCLK frequency. This input must contain either eight or sixteen
clock cycles within the valid enable strobe window. BCLK may be any rate between 128 KHz to 4.096 MHz and can
be discontinuous outside of the enable strobe windows defined by ENA1, ENA2 pins. Incoming PCM data (Rin, Sin)
are sampled on the falling edge of BCLK while outgoing PCM data (Sout, Rout) are clocked out on the rising edge
of BCLK. See Figure 13.
In ST-BUS and GCI operation, connect the system C4 (4.096 MHz) clock to the C4i pin.
2.6 Master Clock (MCLK)
A nominal 20 MHz, continuously-running master clock (MCLK) is required. MCLK may be asynchronous with the
8 KHz frame.
3.0 Microport
The serial microport provides access to all ZL38001 internal read and write registers, plus write-only access to the
bootloadable program RAM (see next section for bootload description.) This microport is compatible with Intel
MCS-51 (mode 0), Motorola SPI (CPOL=0, CPHA=0) and National Semiconductor Microwire specifications. The
microport consists of a transmit/receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (CS) and a
synchronous data clock pin (SCLK).
The ZL38001 automatically adjusts its internal timing and pin configuration to conform to Intel or Motorola/National
requirements. The microport dynamically senses the state of the SCLK pin each time CS pin becomes active (i.e.,
high to low transition). If SCLK pin is high during CS activation, then Intel mode 0 timing is assumed. In this case
DATA1 pin is defined as a bi-directional (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK
is low during CS activation, then Motorola/National timing is assumed and DATA1 is defined as the data transmit pin
while DATA2 becomes the data receive pin. The ZL38001 supports Motorola half-duplex processor mode (CPOL=0
18
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
