ZL38001
Data Sheet
Once the program has been loaded, to begin execution from RAM, bootload mode must be disabled (BOOT bit,
C2=0) and execution from RAM enabled (RAM_ROMb bit, C3=1) by setting the appropriate bits in the BRC register.
During the bootload process, however, ROM program execution (RAM_ROMb bit, C3=0) should be selected. See
Table 5 for the effect of the BRC register settings on Microport accesses and on program execution.
Following program loading and enabling of execution from RAM, it is recommended that users set the software
reset bit in the Main Control (MC) register, to ensure that the device updates the default register values to those of
the new program in RAM. Note: it is important to use a software reset rather than a hardware (RESET=0) reset, as
the latter will return the device to its default settings (which includes execution from program ROM instead of RAM.)
To verify which code revision is currently running, users can access the Firmware Revision Code (FRC) register
(see Register Summary). This register reflects the identity code (revision number) of the last program to run register
initialization (which follows a software or hardware reset.)
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COMMAND/ADDRESS
DATA INPUT/OUTPUT
A0 A1 A2 A3 A4 A5
X
D0 D1 D2 D3 D4 D5 D6 D7
R/W
DATA 1
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SCLK
CS
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This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to ZL38001.
The ZL38001: latches receive data on the rising edge of SCLK
outputs transmit data on the falling edge of SCLK
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The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
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The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
6 bits - Addressing Data
1 bit - Unused
Figure 8 - Serial Microport Timing for Intel Mode 0
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