ZL38001
Data Sheet
COMMAND/ADDRESS ƒ
DATA INPUT
DATA 2
Receive
R/W A5 A4 A3 A2 A1 A0
X
D7 D6 D5 D4 D3 D2 D1 D0
DATA OUTPUT
DATA 1
Transmit
D7 D6 D5 D4 D3 D2 D1 D0
High Impedance
¿
¡
SCLK
CS
Ð
¬
¿
¡
This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to ZL38001.
The ZL38001: latches receive data on the rising edge of SCLK
outputs transmit data on the falling edge of SCLK
¬
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
Ð
ƒ
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
6 bits - Addressing Data
1 bit - Unused
Figure 9 - Serial Microport Timing for Motorola Mode 00 or National Microwire
22
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
