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ZL38001 参数 Datasheet PDF下载

ZL38001图片预览
型号: ZL38001
PDF下载: 下载PDF文件 查看货源
内容描述: 低压声学回声消除器低ERL补偿 [Low-Voltage Acoustic Echo Canceller with Low ERL Compensation]
分类和应用:
文件页数/大小: 47 页 / 646 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL38001  
Data Sheet  
In SSI operation, the frame boundary is determined by the rising edge of the ENA1 enable strobe (see Figure 7).  
The other enable strobe (ENA2) is used for parsing input/output data and it must pulse within 125 microseconds of  
the rising edge of ENA1.  
In SSI operation, the enable strobes may be a mixed combination of 8 or 16 BCLK cycles allowing the flexibility to  
mix 2’s complement linear data on one port (e.g., Rin/Sout) with companded data on the other port (e.g., Sin/Rout).  
Enable Strobe Pin  
Designated PCM I/O Port  
ENA1  
ENA2  
Line Side Echo Path (PORT 1)  
Acoustic Side Echo Path (PORT 2)  
Table 3 - SSI Enable Strobe Pins  
2.3 PCM Law and Format Control (LAW, FORMAT)  
The PCM companding/coding law used by the ZL38001 is controlled through the LAW and FORMAT pins. ITU-T  
G.711 companding curves for µ-Law and A-Law are selected by the LAW pin. PCM coding ITU-T G.711 and Sign-  
Magnitude are selected by the FORMAT pin. See Table 4.  
BCLK  
start of frame (SSI)  
PORT1  
ENA1  
8 or 16 bits  
Rin  
EC  
Sout  
8 or 16 bits  
PORT2  
ENA2  
8 or 16 bits  
Sin  
EC  
8 or 16 bits  
Rout  
outputs = High impedance  
inputs = don’t care  
Note that the two ports are independent so that, for example, PORT1 can operate with 8-bit enable strobes and PORT2 can operate  
with 16-bit enable strobes.  
Figure 7 - SSI Operations  
17  
Zarlink Semiconductor Inc.