ZL38001
Data Sheet
C4i
start of frame (stbus & GCI)
F0i (stbus)
F0i (GCI)
Rin
S 141312 1110 9 8 7 6 5 4 3 2 1 0
PORT1
EC
S 141312 1110 9 8 7 6 5 4 3 2 1 0
Sout
Sin
S 141312 1110 9 8 7 6 5 4 3 2 1 0
PORT2
EC
S 141312 1110 9 8 7 6 5 4 3 2 1 0
Rout
outputs = High impedance
inputs = don’t care
ST-BUS/GCI Mode 4 allows 16 bit 2’s complement linear data to be transferred using ST-BUS/GCI I/O timing. Note that PORT1 and
PORT2 need not necessarily both be in mode 4.
Figure 6 - ST-BUS and GCI 16-Bit 2’s Complement Linear PCM I/O (Mode 4)
PORT1
ST-BUS/GCI Mode
Selection
PORT2
Rin/Sout
Sin/Rout
Enable Pins
Enable Pins
MD1
ENA1
MD2
ENA2
0
0
Mode 1. 8 bit companded PCM I/O on timeslot 0
Mode 2. 8 bit companded PCM I/O on timeslot 2.
0
0
0
1
1
0
0
1
1
0
Mode 3. 8 bit companded PCM I/O on timeslot 2.
Includes D & C channel bypass in timeslots 0 & 1.
1
1
Mode 4. 16-bit 2’s complement linear PCM I/O on
timeslots 0 & 1.
1
1
Table 2 - ST-BUS & GCI Mode Select
2.2 SSI Operation
The SSI PCM interface consists of data input pins (Rin, Sin), data output pins (Sout, Rout), a variable rate bit clock
(BCLK), and two enable pins (ENA1, ENA2) to provide strobes for data transfers. The active high enable may be
either 8 or 16 BCLK cycles in duration. Automatic detection of the data type (8 bit companded or 16-bit 2’s
complement linear) is accomplished internally. The data type cannot change dynamically from one frame to the
next.
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
