ZL30402
Data Sheet
Address: 1A H
Bit Name
Functional Description
Default
7-0 FPOA7 - 0 Fine Phase Offset Adjustment. This register allows phase offset adjustment of
00000
all output clocks and frame pulses (C16o, C8o, C4o, C2o, F16o, F8o, F0o, C155,
C19o, C34/44, C1.5o, C6o) relative to the active input reference. The adjustment
can be positive (advance) or negative (delay) with a nominal step size of 477 ps
(61.035 ns / 128). The rate of phase change is limited to 885 ns/s for FCS = 1 and
41 ns in 1.326 ms for FCS = 0 selections. The phase offset value is a signed 2’s
complement number e.g.:
000
Advance: +1 step = 01H, +2 steps = 02H, +127 steps = EFH
Delay: -1 step = FFH, -2 steps = FEH, -128 steps = 80H
Example: Writing 08H advances all clocks by 3.8 ns and writing F3H delays all
clocks
Table 15 - Fine Phase Offset Register (R/W)
Address: 20 H
Bit
Name
RSV
Functional Description
7-5
4-3
Reserved.
InpFreq1- Input Frequency. These two bits identify the Primary Reference Clock frequency.
0
- 00 = 19.44 MHz
- 01 = 8 kHz
- 10 = 1.544 MHz
- 11 = 2.048 MHz
2
1
RSV
PAH
Reserved.
Primary Acquisition PLL Holdover. This bit goes high whenever the Acquisition PLL
enters Holdover mode. Holdover mode is entered when the reference frequency is
- lost completely
- drifts more than ±30 000 ppm off from the nominal frequency
- a large phase hit occurs on the reference clock.
0
PAFL
Primary Acquisition PLL Frequency Limit. This bit goes high whenever the Acquisition
PLL exceeds its capture range of ±104 ppm. This bit can flicker high in the event of a large
excursion of still tolerable input jitter.
Table 16 - Primary Acquisition PLL Status Register (R)
26
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
