ZL30402
Data Sheet
Address: 06 H
Bit
7-4
3
Name
RSV
Functional Description
Default
0000
0
Reserved.
OffEn
Offset Enable. Set high to enable programmable phase offset
adjustments (C16 Phase Offset Adjustment and C1.5 Phase Offset
Adjustment) between the input reference and the generated clocks.
2 - 0
C16POA10
to
000
C16 Phase Offset Adjustment. These three bits (most significant) in
conjunction with the eight bits of Phase Offset Register 1 allow for
phase shifting of all clocks and frame pulses that are derived from the
C16 clock (C8o, C4o, C2o, F16o, F8o, F0o). The phase offset is an
unsigned number in a range from 0 to 2047. Each increment by one
represents phase-offset advancement by 61.035 ns with respect to
the input reference signal. The phase offset is a two-byte value and it
must be written in one step increments. For example: four writes are
required to advance clocks by 244 ns from its current position of 22H:
write 23H, 24H, 25H, 26H. Writing numbers in reverse order will delay
clocks from their present position.
C16POA8
Table 8 - Phase Offset Register 2 (R/W)
Address: 07 H
Bit
Name
Functional Description
Default
7-0
C16POA7
to
C16 Phase Offset Adjustment. The eight least significant bits of the
phase offset adjustment word. See the Phase Offset Register 2 for
details.
0000
0000
C16POA0
Table 9 - Phase Offset Register 1 (R/W)
Address: 0F H
Bit
Name
Functional Description
7-4
ID7 - 4
Device Identification Number. These four bits represent the device part number.
The ID number for ZL30402 is 0010.
3-0
ID3 - 0
Device Revision Number. These bits represent the revision number. Number
starts from 0001.
Table 10 - Device ID Register (R)
23
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
