ZL30402
Data Sheet
Address: 11 H
Bit
Name
Functional Description
Default
7
6
RSV
RSV
Reserved.
0
0
Reserved.
5-3
C1.5POA2 C1.5 Phase Offset Adjustment. These three bits allow for changing of
000
to
the phase offset of the C1.5o clock relative to the active input reference.
C1.5POA0 The phase offset is an unsigned number in a range from 0 to 7. Each
increment by one represents phase-offset advancement by 80.96 ns.
Example: Writing 010 advances C1.5 clock by 162 ns. Successive writing
of 001 delays this clock by 80.96 ns from its present position
2-0
RSV
Reserved.
000
Table 11 - Control Register 3 (R/W)
Address: 13 H
Bit
Name
Functional Description
Default
7
6
5
RSV
RSV
Reserved.
Reserved.
0
0
C16dis 16.384 MHz Clock Disable. When set high, this bit tristates the 16.384 MHz clock
0
0
0
0
0
0
output.
4
3
2
1
0
C8dis
C4dis
C2dis
8.192 MHz Clock Disable. When set high, this bit tristates the 8.192 MHz clock
output.
4.096 MHz Clock Disable. When set high, this bit tristates the 4.096 MHz clock
output.
2.048 MHz Clock Disable. When set high, this bit tristates the 2.048 MHz clock
output.
C1.5dis 1.544 MHz Clock Disable. When set high, this bit tristates the 1.544 MHz clock
output.
RSV
Reserved.
Table 12 - Clock Disable Register 1 (R/W)
24
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
