ZL30402
Data Sheet
5.1.2 Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL
The NORMAL to AUTO-HOLDOVER to NORMAL transition will usually happen when the Network Element loses
its single reference clock unexpectedly or when it has two references but switching to the secondary reference is
not a desirable option (unless primary reference is lost without chance of quick recovery).
The sequence starts with the unexpected failure of a reference signal shown as transition OK --> FAIL in Figure 7
"Transition from Free-Run to Normal Mode" at a time when ZL30402 operates in Normal mode. This failure is
detected by the active Acquisition PLL based on the following FAIL criteria:
•
Frequency offset on 8 kHz, 1.544 MHz, 2.048 MHz and 19.44 MHz reference clocks exceeds ±30000 ppm
(±3%).
•
Single phase hit on 1.544 MHz, 2.048 MHz and 19.44 MHz exceeds half of the cycle of the reference clock.
After detecting any of these anomalies on a reference clock the Acquisition PLL will switch itself into Holdover mode
forcing the Core PLL to automatically switch into the Auto Holdover state. This condition is flagged by LOCK = 0
and HOLDOVER = 1.
MS2, MS1 == 01 OR
RefSel change
Ref: FAIL --> OK &
MS2, MS1 == 00 &
AHRD=1 &
NORMAL
(LOCKED)
00
MHR=0 -->1 then 1-->0
{MANUAL}
Ref: OK &
Ref: OK --> FAIL &
MS2, MS1 == 00
{AUTO}
Ref: FAIL --> OK &
MS2, MS1 == 00 &
AHRD=0
MS2, MS1 == 00
{AUTO}
MS2, MS1! = 10
RESET == 1
{AUTO}
AUTO
HOLD-
OVER
RefSel Change
FREE-
RUN
10
HOLD-
OVER
01
RESET
Automatic return to NORMAL: AHRD=0
OR
Manual return to NORMAL: AHRD=1 & MHR= 0-->1 then 1-->0
MS2, MS1 == 10 forces
unconditional return from
any state to Free-run
Figure 8 - Automatic Entry into Auto Holdover State and Eecovery into Normal mode
There are two possible returns to Normal mode after the reference signal is restored:
•
With the AHRD (Automatic Holdover Return Disable) bit set to 0. In this case the Core PLL will automatically
return to the Normal state after the reference signal recovers from failure. This transition is shown on the
state diagram as a FAIL --> OK change. This change becomes effective when the reference is restored and
there have been no phase hits detected for at least 64 clock cycles for 1.544/2.048 MHz reference, 512
clock cycles for 19.44 MHz reference and 1 clock cycle for 8 kHz reference.
•
With the AHRD bit set to high to disable automatic return to Normal and the change of MHR (Manual
Holdover Release) bit from 0 to 1 to trigger the transition from Auto Holdover to Normal. This option is
provided to protect the Core PLL against toggling between Normal and Auto Holdover states in case of an
intermittent quality reference clock. In the case when MHR has been changed when the reference is still not
available (Acquisition PLL in Holdover mode) the transition to Normal state will not occur and MHR 0 to 1
transition must be repeated.
This transition from Auto Holdover to Normal mode is performed as “hitless” reference switching.
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
