PDSP16256/A
Filter Accuary
Input data and coefficients are both represented by 16-
bit two’s complement numbers. The coefficients are
converted to twelve bits by rounding towards zero. This
is achieved as follows. If the coefficient is positive then
theleastsignificant4bitsarediscarded. Ifthecoefficient
is negative then the logical ‘OR’ of the least significant 4
bits are added to the remainder of the word. Twelve bit
coefficients can be used directly provided the least
significant four bits are set to zero.
INPUT DATA
COEFFICIENT
ADDER
The FIR filter results are calculated using a multiplier
accumulator structure as shown in Fig. 10. The trunca-
tion and word growth allowed for in the data path are
explained in Fig. 10. The 16-bit data and 12-bit coeffi-
cient inputs (each with one sign bit before the binary
point), are presented to the multiplier. This produces a
28-bitresultwithtwobitsbeforethebinarypoint.Produc-
ing the full 28-bit result ensures that if both the data and
coefficients are set to logic 1 a valid result is generated.
Prior to entering the accumulator the least significant 4
bitsofthemultiplierresultaretruncatedandtheresulting
24 bits sign extended to 32 bits. The final accumulator
result is 32 bits with 10 bits before the binary point. Thus
9bitsofwordgrowthareallowedwithintheaccumulator.
All accumulator bits are made available on the output
pins.
ACCUMULATOR
RESULT
Figure. 10 Multiplier Accumulator
In cascade mode the middle 16 bits from the network A
accumulator are fed round to the network B data inputs,
see Fig. 11.
INPUT DATA
COEFFICIENT
S
S
S
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11
Multiplication producing a 28-bit result
MULTIPLIER RESULT
0
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14
-22 -23 -24 -25 -26
Sign extended to 32 bits, least significant 4 bits truncated
ACCUMULATOR RESULT
S
S
S
S
S
S
S
3
S
2
S
1
0
0
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14
-22
-22
ACCUMULATOR RESULT
S
8
7
6
5
4
These bits are passed to filter network B during cascade mode
Figure. 11 Filter accuracy
10