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PDSP16256A 参数 Datasheet PDF下载

PDSP16256A图片预览
型号: PDSP16256A
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程FIR滤波器 [Programmable FIR Filter]
分类和应用:
文件页数/大小: 25 页 / 205 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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PDSP16256/A  
Dual Indipendant Filter Options  
length is selected using control register bits 14 and 13 as  
summarised in Table 4, which also shows the resulting  
latency. As in single filter mode normal or decimate-by-  
two operation can be selected using control register bit  
12.  
When operating as two independent filters the device  
accepts 16 bit data on both the DA and DB buses at the  
selected sample rate, see Fig. 8. Results are available  
from both the F and X buses. The F bus may be tristated  
using the OEN input. Signal OEN is registered onto the  
device and does not therefore take effect until the first  
SCLK rising edge  
Dual Cascaded Filter Options  
When operating as two cascaded filters the device ac-  
cepts 16 bit data on the DA bus at the selected sample  
rate. Results are presented on the 32-bit X bus, see Fig.  
9. Each filter must be configured in the same manner.  
Multiple device expansion is not possible in this mode.  
Each filter must be configured in the same manner, and  
multiple device expansion is not possible due to the pin  
re-organization. The latter requirement can, of course,  
still be satisfied by several devices configured as single  
filters.  
Dual cascaded filter mode is selected by setting control  
register bit 15 to a zero and bit 4 to a one. The required  
filter length is selected using control register bits 14 and  
13 as summarised in Table 4, which also shows the  
resulting latency. The decimate-by-two option is not  
available in this mode.  
The data for the second filter network is extracted as the  
middle16bitsfromthefirstnetworksaccumulatedresult.  
Forsuccessfuloperationthefirstfilternetworkmusthave  
unity gain. See the section on filter accuracy for more  
details.  
Dual independent filter mode is selected by setting  
control register bits 15 and 4 to a zero. The required filter  
CR  
Input  
Output  
Rate  
Filter  
Length  
Setup  
Latency  
1413 12 Rate  
Ind Cas  
0 0 0 SCLK  
0 0 1 SCLK  
0 1 0 SCLK/2  
0 1 1 SCLK/2  
1 0 0 SCLK/4  
1 0 1 SCLK/4  
1 1 0 SCLK/8  
SCLK  
8 Taps  
16 Taps  
16 Taps  
32 Taps  
32 Taps  
64 Taps  
64 Taps  
16  
17  
16  
18  
20  
24  
24  
27  
-
28  
-
SCLK/2  
SCLK/2  
SCLK/4  
SCLK/4  
SCLK/8  
SCLK/8  
36  
The cascade option is used to increase the stop band  
rejection in a practical filter application. Theoretically,  
increasingthenumberoftapsinanFIRfilterwillincrease  
the stop band rejection, but this assumes floating point  
calculationswithnoaccuracylimitations.Inpractice,with  
fixed point arithmetic, better performance is achieved  
with two smaller filters in series.  
-
40  
Table 4. Dual Filter options  
DA15:0  
F31:0  
OEN  
DA15:0  
F31:0  
OEN  
NETWORK  
A
NETWORK  
A
DUAL  
MODE  
DUAL  
MODE  
MUX  
MUX  
NETWORK  
B
NETWORK  
B
SINGLE  
MODE  
SINGLE  
MODE  
DB15:0  
X31:0  
DB15:0  
X31:0  
Figure. 8 Dual independent filter bus utilisation  
Figure. 9 Dual cascaded filter bus utilisation  
9