PDSP16256/A
SPEED MODE 0 (Data input and output at f ) CR14:13 = 00, CR12 = 0. CLKOP held high.
SCLK
SCLK
31
32
33
1
2
3
16
17
18
34
35
FEN
DA15:0
A
B
C
F31:0
A′′
B′′
C′′
D′′
E′′
A′
B′
C′
CLKOP
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 16
Valid result contains
the first 16 data points
available after edge 31
SPEED MODE 1 (Data input and output at half f ) CR14:13 = 01, CR12 = 0
SCLK
SCLK
78
79
80
1
2
3
16
17
18
81
82
FEN
DA15:0
A
B
F31:0
A′′
B′′
C′′
A′
B′
CLKOP
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 16
Valid result contains
the first 32 data points
available after edge 78
SPEED MODE 2 (Data input and output at a quarter f ) CR14:13 = 10, CR12 = 0
SCLK
SCLK
272 273 274 275 276
1
2
3
4
5
20
21 22
23 24
FEN
DA15:0
A
B
F31:0
A′
B′
A′′
B′′
CLKOP
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 20
Valid result contains
the first 64 data points
available after edge 272
SPEED MODE 3 (Data input and output at an eighth f ) CR14:13 = 11, CR12 = 0
SCLK
SCLK
1040 1041 1042 1043
1
2
3
4
5
6
7
8
9
24
25 26
27 28 29 30
31 32
FEN
A
B
DA15:0
F31:0
A′
B′
A′′
CLKOP
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 24
Valid result contains
the first 128 data points
available after edge 1040
SPEED MODE 1 Decimating (Datainputathalf f
andoutputataquarterf )CR14:13=01,CR12=1.
SCLK
SCLK
SCLK
142
143
144
1
2
3
18
19
20
21
22
145
FEN
DA15:0
A
B
F31:0
B′
B′′
CLKOP
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 18
Valid result contains
the first 64 data points
available after edge 142
Figure. 7 Single Filter timing diagrams
8
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