PDSP16256/A
SCLK
00
01
00
01
VALID ADDR
VALID ADDR
00
A7:0
LOAD MASTER CONTROL LOAD FIRST COEFFICIENT
REGISTER
LOAD LAST COEFFICIENT
CCS
RES
BUSY
Fig. 15a EPROM load sequence
SCLK
A7:0
CCS
FE
FF
00
01
00
01
FE
FF
00
01
00
01
0000
0001
0001
0010
C15:12
LOAD LAST
MASTER
COEFFICIENT
LOAD SLAVE 1
CONTROL
REGISTER
LOAD SLAVE 1
COEFFICIENTS
LOAD LAST
SLAVE 1
COEFFICIENT
LOAD SLAVE 2
CONTROL
REGISTER
LOAD SLAVE 2
COEFFICIENTS
Fig. 15b EPROM load sequence for a cascaded system
Figure. 15 EPROM load sequence timing diagrams
(2 SLAVES)
PDSP16256
0010
GND
GND
GND
C11:8
CS
EPROM
LSB
A7:0
ADDRESS
CCS
MASTER
EPROM
BYTE
WEN
MSB
C15:12
C7:0
DATA
PDSP16256
SLAVE 1
0001
GND
C11:8
CS
A7:0
CCS
V
EPROM
BYTE
WEN
DD
C15:12
C7:0
GND
PDSP16256
SLAVE 2
0010
GND
C11:8
CS
A7:0
CCS
V
EPROM
BYTE
WEN
DD
C15:12
C7:0
GND
Figure. 16 Three device auto EPROM load
14
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