PDSP16256/A
DATA
OUT
DATA
IN
DATA
DELAY LINE
DATA
DELAY LINE
DATA
DELAY LINE
DATA
DELAY LINE
COEFF
RAM
COEFF
RAM
COEFF
RAM
COEFF
RAM
ACCUMULATE
EXPANSION
IN
RESULT
OUT
ADDER
ADDER
ADDER
ADDER
21
21
21
21
Z
Z
Z
Z
Figure. 5 Filter network diagram
Single Filter Options
the higher frequency components present in the input.
The Nyquist criterion, specifying that the sampling rate
must be at least double the highest frequency compo-
nent, can still then be satisfied even though the sampling
rate has been halved.
When operating as a single filter the device accepts data
on the 16-bit DA bus at the selected sample rate, see
Figs. 5 and 6. Results are presented on the 32-bit F bus,
whichmaybetristatedusingthe OEN input.Signal OEN is
registered onto the device and does not therefore take
effect until the first SCLK rising edge. Devices may be
cascaded this allows filters with more taps than available
from a single device. To accomplish this two further
buses are utilised. The DB bus presents the input data to
the next device in cascade after the appropriate delay,
while, partial results are accepted on the X bus.
The system clock latency for a single device is shown in
Table3.Thisisdefinedasthedelayfromaparticulardata
sample being available on the input pins to the first result
including that input appearing on the output pins. It does
not include the delay needed to gather N samples, for an
N tap filter, before a mathematically correct result is
obtained.
Singlefiltermodeisselectedbysettingcontrolregisterbit
15 to a one. The required filter length is then selected
using control register bits 14 and 13 as summarised in
Table 3. The options define the number of times each
multiplier accumulator is used per sample clock period.
This can be once, twice, four times, or eight times.
DA15:0
F31:0
OEN
NETWORK
A
In addition a normal/decimate bit (CR12) allows the filter
length to be doubled at any sample rate. This is possible
when the filter coefficients are selected to produce a low
passfilter,sincethefilteredoutputwouldthennotcontain
DUAL
MODE
MUX
CR
Input
Output
Rate
Filter
Length
Setup
Latency
14 13 12 Rate
NETWORK
B
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
SCLK
SCLK
SCLK
16 Taps
32 Taps
32 Taps
64 Taps
64 Taps
128 Taps
128 Taps
16
17
16
18
20
24
24
SCLK/2
SCLK/2
SCLK/4
SCLK/4
SCLK/8
SCLK/8
SCLK/2
SCLK/2
SCLK/4
SCLK/4
SCLK/8
SINGLE
MODE
DB15:0
X31:0
Table 3 Single Filter options
Figure. 6 Single Filter bus utilisation
7
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