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PDSP16256A 参数 Datasheet PDF下载

PDSP16256A图片预览
型号: PDSP16256A
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程FIR滤波器 [Programmable FIR Filter]
分类和应用:
文件页数/大小: 25 页 / 205 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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PDSP16256/A  
DA15:0  
F31:0  
OEN  
SCLK  
FRUN  
SWAP  
A7:0  
NETWORK  
A
C15:0  
CCS  
WEN  
CS  
DUAL  
MODE  
COEFFICIENT  
STORAGE  
AND  
MUX  
BYTE  
EPROM  
FEN  
CONTROL  
NETWORK  
B
DFEN  
DCLR  
RES  
SINGLE  
MODE  
CLKOP  
BUSY  
DB15:0  
X31:0  
Figure. 4 Block Diagram  
Operational Overview  
The PDSP16256 is an application specific FIR filter for  
use in high performance digital signal processing  
systems. Sampling rates can be up to 25MHz. The  
device provides the filter function without any software  
development, and the options are simply selected by  
loading a control register. The device can be user  
configured as either a single filter, or as two separate  
filters. The latter can provide two independent filters for  
the in-phase and quadrature channels after IQ splitting,  
or can provide two filters in cascade for greater stop  
band rejection.  
through’ are not permissible in the system.  
Coefficients can be loaded from a host system using a  
conventional peripheral interface and separate data  
bus. Alternatively, they can be loaded as a complete set  
from a byte wide EPROM. The device produces  
addresses for the EPROM and a BUSY output indicates  
that the transfer is occurring. Up to sixteen devices can  
have their coefficients supplied from a single EPROM.  
These devices need not necessarily be part of the same  
filter network.  
Each of the filter networks shown in Fig. 4 contains eight  
systolic multiplier accumulator stages; an example with  
four stages is shown in Fig. 5. Input data flows through  
thedelaylinesandispresentedformultiplicationwiththe  
requiredcoefficient. Thisisaddedtoeitherthelastresult  
from this accumulator or the result from the previous  
accumulator.Thefilterresultsprogressalongtheadders  
at the data sample rate. If the sample rate equals SCLK  
dividedbyfour,forexample,thentheaccumulatedresult  
is passed onto the next stage every fourth cycle. The  
structure described is highly efficient when used to  
calculate filtered results from continuous input data.  
A comprehensive digital filter design program is  
availableforPCcompatiblemachines. Thiswilloptimise  
the filter coefficients for the filter type required and  
number of taps available at the selected sample rate  
within the PDSP16256 device. An EPROM file can be  
automatically generated in Motorola S-record format.  
The device operates from a system clock, with rates up  
to 25MHz. This clock must be 1, 2, 4, or 8 times the  
required sampling frequency, with the higher  
multiplication rates producing longer filter networks at  
the expense of lower sampling rates. Devices can be  
connected in cascade to produce longer filter lengths.  
This can be accomplished without the need for any  
additional external data delays, and all the single device  
options remain available.  
Continuous inputs are accepted, and continuous results  
produced after the internal pipeline delay. Connection  
can be made directly to an A-D converter. The filter  
operation can be synchronised to a Filter Enable signal  
(FEN) whose positive going edge marks the first data  
sample. Theinternalmultiplieraccumulatorarraycanbe  
cleared with a dedicated input. This is necessary if  
erroneous results obtained during the normal data ‘flush  
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