MVTX2801
Data Sheet
2
CPU
Addr
(Hex)
I C
Register
Description
R/W
Default
Notes
Addr
(Hex)
TOSPMH
AVDM
TOSDML
BMRC
UCC
TOS Priority Map High
508
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
046
fa
VLAN Discard Map
TOS Discard Map
509
047
048
049
04A
04B
04C
04D
04E
04F
050
051
052
053
054
055-084
NA
00
00
00
07
48
00
26
37
00
00
00
00
00
00
50A
50B
50C
50D
50E
50F
Broadcast/Multicast Rate Control
Unicast Congestion Control
Multicast Congestion Control
Port Reservation for 10/100 Ports
Port Reservation for Giga Ports
Share FCB Size
MCC
PR100
PRG
SFCB
510
C2RS
Class 2 Reserved Size
Class 3 Reserved Size
Class 4 Reserved Size
Class 5 Reserved Size
Class 6 Reserved Size
Class 7 Reserved Size
QOS Control (N=0 - 2F)
QOS Control (N=30 - 82)
WRED Rate Control 0
511
C3RS
512
C4RS
513
C5RS
514
C6RS
515
C7RS
516
QOSC”N”
QOSC”N”
RDRC0
RDRC1
517-546
547-599
59A
59B
085
086
8e
68
WRED Rate Control 1
6. MISC Configuration Register
MII_OP0
MII_OP1
FEN
MII Register Option 0
600
601
602
603
604
605
606
607
608
609
60B
60C
60D
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
0B1
0B2
0B3
N/A
N/A
N/A
N/A
N/A
N/A
0B4
0C5
0BB
0BC
00
00
10
00
00
00
00
00
00
38
00
00
00
MII Register Option 1
Feature Registers
MIIC0
MII Command Register 0
MII Command Register 1
MII Command Register 2
MII Command Register 3
MII Data Register 0
MIIC1
MIIC2
MIIC3
MIID0
MIID1
MII Data Register 1
RO
LED
LED Control Register
R/W
R/W
R/W
R/W
CHECKSUM
LEDUSER0
LEDUSER1
EEPROM Checksum Register
LED User Define Register 0
LED User Define Register 1
Table 7 - MVTX2801 Register Description (continued)
29
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
