MT9196
Data Sheet
ADDRESS = 0Dh RESERVED
Control Register 1
ADDRESS = 0Eh WRITE/READ VERIFY
Power Reset Value
100X X000
PD
7
Tfhp
6
DialEN
5
-
B2/B1 RxMute TxMute
-
4
3
2
1
0
PD
When high, the crystal oscillator and FDI blocks are powered down. When low, the oscillator and FDI circuits are active.
Tfhp
When High, an additional highpass function (passband beginning at 400 Hz) is inserted into the transmit path. When
low, this highpass filter is disabled.
DialEN
When high, a first order lowpass filter is inserted into the receive path (3 dB = 1.2 kHz). When low, this lowpass filter is
disabled.
B2/B1
When high, the receive Filter/CODEC operates on the B2-Channel. When low, the receive Filter/CODEC operates on
the B1-Channel. This control bit has significance only for ST-BUS operation and is ignored for SSI operation.
RxMUTE
TxMUTE
When high the received PCM stream is interrupted and replaced with quiet code; thus forcing the receive path into a
mute state. When low the full receive path functions normally.
When high the transmit PCM stream is interrupted and replaced with quiet code; thus forcing the output code into a
mute state (only the output code is muted, the transmit microphone and transmit Filter/CODEC are still functional).
When low the full transmit path functions normally.
Control Register 2
ADDRESS = 0Fh WRITE/READ VERIFY
Power Reset Value
Smag/
CCITT
0X00 00XX
-
-
-
RST
7
A/µ
TxINC
2
RxINC
3
6
5
4
1
0
RST
When high, a software reset occurs performing the same function as the hardware reset (PWRST) except that the
microport and watchdog circuitry are not affected. A software reset can be removed only by writing this bit low or by a
PWRST. When low, the reset condition is removed.
A/µ
When high, A-Law (de)coding is selected for the Filter/CODEC and DTMF generator circuits. When low, µ-Law
(de)coding is selected for these circuits.
Smag/CCITT
When high, sign-magnitude code assignment is selected for the CODEC input/output. When low, CCITT code
assignment is selected for the CODEC input/output; true sign, inverted magnitude (µ-Law) or true sign, alternate digit
inversion (A-Law).
RxINC
TxINC
When high, the receiver driver nominal gain is set at -9.6 dB. When low, this driver nominal gain is set at -12.1 dB.
When high, the transmit amplifier nominal gain is set at 15.3 dB. When low, this amplifier nominal gain is set at
6.0 dB.
Note: Bits marked "-" are reserved bits and should be written with logic "0".
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
