MT9196
Data Sheet
Power-up/down & PWRST/Software Reset
While the IDPC is held in PWRST no device control or functionality is possible. While in software reset (RST=1,
address 0Fh) only the microport and watchdog are functional. Software reset can only be removed by writing RST
logic low or by the PWRST pin.
After Power-up reset (PWRST) or software reset (RST) all control bits assume their default states; µ-Law
functionality, usually 0 dB programmable gains and all sections of IDPC, except the microport and watchdog, into
powered down states. This is the low power, stand-by condition. This includes:
•
The receive output drive transducers. All transducer output drivers are powered down forcing the output
signals into tri-state. Output drivers (handset, handsfree-speaker, AUXout) are powered up/down individually
as required by the state of the programmed bits in the Receive Path Control Register (address 13h)
•
The transmit and receive filters and CODEC. All clocks for this circuit block are disabled. The complete
section is automatically powered up as required by the programmed bits in the Transmit and Receive Path
Control registers (addresses 12h and 13h). Whenever all path control selections are off this section is
powered down. The CODEC and transmit/ receive filters cannot be powered up individually.
•
•
The VRef and VBias circuits. Reference and Bias voltage drivers are tri-stated during power down causing
the voltage at the pins to float. This circuit block is automatically powered up/down as it is required by either
the Filter/CODEC or the transducer driver circuits. Whenever all path control selections are off this section is
powered down. If the AUXin path to (any combination of the) output transducer drivers is selected then the
VRef/VBias circuit is powered up but the Filter/CODEC circuit is not.
The FDI and oscillator circuits. After PWRST, the device assumes SSI operation with Dout tri-stated while
there is no strobe active on STB. If a valid strobe is supplied to STB, then Dout will be active, during the
defined channel, supplying quiet code as defined in Table 1. If the device is switched to ST-BUS operation
following PWRST, the entire Dout stream will be tri-stated until an active transmit channel is programmed. As
well, following PWRST, the oscillator circuit is disabled and all timing for the IDPC functional blocks is halted.
A clock signal applied to the MCL pin is prevented from entering further into the IDPC when the
Asynch/Synch bit is logic “1”.
To power up the FDI and oscillator circuits the PD bit of Control Register 1 (address 0Eh) must be cleared.
To attain complete power-down from a normal operating condition, write all “0s” to the Transmit and Receive Path
Control Registers (address 12h and 13h), set PD to logic 1 at address 0Eh, and Asynch/Synch to logic 1 at address
10h.
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
