MT9196
Data Sheet
Register Summary
ADDRESSES = 00h to 09h ARE RESERVED
ADDRESS = 0Ah WRITE/READ VERIFY
Filter Codec Control Register 1
Power Reset Value
X000 X000
-
-
RxFG2 RxFG1 RxFG0
TxFG2 TxFG1 TxFG0
7
6
5
4
3
2
1
0
Receive Gain
Setting (dB)
Transmit Gain
Setting (dB)
RxFG2
RxFG1
RxFG0
TxFG2
TxFG1
TxFG0
(default) 0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(default) 0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-1
-2
-3
-4
-5
-6
-7
1
2
3
4
5
6
7
RxFGn = Receive Filter Gain n
TxFGn = Transmit Filter Gain n
Filter Codec Control Register 2
ADDRESS = 0Bh WRITE/READ VERIFY
Power Reset Value
0010 X000
-
Gain3 Gain2 Gain1 Gain0
STG2
2
STG1 STG0
7
6
5
4
3
1
0
Speaker Gain (dB)
Side-tone Gain
Setting (dB)
Gain2
Gain1
Gain0
STG2
STG1
STG0
Gain3 = 1
16
Gain3 = 0
8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(default) OFF
-9.96
-6.64
-3.32
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
12
8
4
0
4
-4
0
-8
-4
-8
-12
-12
-16
-20
3.32
6.64
9.96
STGn = Side-tone Gain n
ADDRESS = 0Ch RESERVED
Note: Bits marked "-" are reserved bits and should be written with logic "0".
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
