MT90826
Data Sheet
transferred directly to the parallel-to-serial converter. This data will be output on the ST-BUS streams in every frame
until the data is changed by the microprocessor.
The three most significant bits of the connection memory controls the following for an output channel: message or
connection mode, constant or variable delay mode, enables/tristate the ST-BUS output drivers and bit error test
pattern enable. If an output channel is set to a high-impedance state by setting the OE bit to zero in the connection
memory, the ST-BUS output will be in a high impedance state for the duration of that channel. In addition to the per-
channel control, all channels on the ST-BUS outputs can be placed in a high impedance state by pulling the ODE
input pin low and programming the output stand by (OSB) bit in the control register to low. This action overrides the
individual per-channel programming by the connection memory bits. See Table 2 for detail.
The connection memory data can be accessed via the microprocessor interface through the D0 to D15 pins. The
addressing of the device internal registers, data and connection memories is performed through the address input
pins and the Memory Select (MS) bit of the control register.
2.3 Clock Timing Requirements
The master clock (CLK) frequency must be either at 8.192 MHz or 16.384 MHz for serial data rate of 2.048, 4.096,
8.192 and 16.384 Mbps; see Table 6 for the selections of the master clock frequency.
3.0 Switching Configurations
The MT90826 maximum non-blocking switching configurations is determined by the data rates selected for the
serial inputs and outputs. The switching configuration is selected by three DR bits in the control register. See Table
5 and Table 6.
8 Mbps mode (DR2=0, DR1=0, DR0=0)
When the 8 Mbps mode is selected, the device is configured with 32-input/32-output data streams each having 128
64 Kbps channels. This mode allows a maximum non-blocking capacity of 4,096 x 4,096 channels. Table 1
summarizes the switching configurations and the relationship between different serial data rates and the master
clock frequencies.
16 Mbps mode (DR2=0, DR1=0, DR0 =1)
When the 16 Mbps mode is selected, the device is configured with 16-input/16-output data streams each having
256 64 Kbps channels. This mode allows a maximum non-blocking capacity of 4,096 x 4,096 channels.
4 Mbps and 8 Mbps mode (DR2=0, DR1=1, DR0=0)
When the 4 Mbps and 8 Mbps mode is selected, the device is configured with 32-input/32-output data streams.
STi0-15/STo0-15 have a data rate of 4 Mbps and STi16-31/STo16-31 have a data rate of 8 Mbps. This mode allows
a maximum non-blocking capacity of 3,072 x 3,072 channels. The MT90826 is capable of rate conversion, allowing
4 Mbps input to be converted to 8 Mbps output and vice versa.
16 Mbps and 8 Mbps mode (DR2=0, DR1=1, DR0=1)
When the 16 Mbps and 8 Mbps mode is selected, the device is configured with 20-input/20-output data streams.
STi0-11/STo0-11 have a data rate of 16 Mbps and STi12-19/STo12-19 have a data rate of 8 Mbps. This mode
allows a maximum non-blocking capacity of 4,096 x 4,096 channels. The MT90826 is capable of rate conversion,
allowing 16 Mbps input to be converted to 8 Mbps output and vice versa.
4 Mbps mode (DR2=1, DR1=0, DR0=0)
When the 4 Mbps mode is selected, the device is configured with 32-input/32-output data streams each having 64
64 Kbps channels. This mode allows a maximum non-blocking capacity of 2,048 x 2,048 channels.
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Zarlink Semiconductor Inc.
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