MT90826
Data Sheet
the output data position up to 45ns to compensate for the output delay caused by excessive output loading
conditions. See Figure 7 “Examples for Frame Output Offset Timing”.
Serial Interface Mode
Input Stream
Input Data Rate
Output Stream
Output Data Rate
8 Mbps
16 Mbps
STi0-31
STi0-15
STi0-15
STi15-31
STi0-11
STi12-19
STi0-31
STi0-15
STi16-31
STi0-31
8 Mbps
16 Mbps
4 Mbps
8 Mbps
16 Mbps
8 Mbps
4 Mbps
2 Mbps
4 Mbps
2 Mbps
STo0-31
STo0-15
STo0-15
STo16-31
STo0-11
STo12-19
STo0-31
STo0-15
STo16-31
STo0-31
8 Mbps
16 Mbps
4 Mbps
8 Mbps
16 Mbps
8 Mbps
4 Mbps
2 Mbps
4 Mbps
2 Mbps
4 Mbps and 8 Mbps
16 Mbps and 8 Mbps
4 Mbps
2 Mbps and 4 Mbps
2 Mbps
Table 1 - Stream Usage under Various Operation Modes
ODE pin
OSB bit in Control register
OE bit in Connection Memory
ST-BUS Output Driver
0
X
1
0
1
0
X
0
1
1
X
High-Z
Per Channel High-Z
Enable
0
1
1
Enable
1
Enable
Table 2 - Output High Impedance Control
The microport interface is compatible with Motorola non-multiplexed buses. Connection memory locations may be
directly written to or read from; data memory locations may be directly read from. A DTA signal is provided to hold
the bus until the asynchronous microport operation is queued into the device.
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Location
Control Register, CR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Frame Alignment Register, FAR
Input Offset Selection Register 0, DOS0
Input Offset Selection Register 1, DOS1
Input Offset Selection Register 2, DOS2
Input Offset Selection Register 3, DOS3
Input Offset Selection Register 4, DOS4
Table 3 - Address Map for Registers (A13 = 0)
13
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
