欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT90826AG 参数 Datasheet PDF下载

MT90826AG图片预览
型号: MT90826AG
PDF下载: 下载PDF文件 查看货源
内容描述: 四数字开关 [Quad Digital Switch]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 46 页 / 571 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
 浏览型号MT90826AG的Datasheet PDF文件第8页浏览型号MT90826AG的Datasheet PDF文件第9页浏览型号MT90826AG的Datasheet PDF文件第10页浏览型号MT90826AG的Datasheet PDF文件第11页浏览型号MT90826AG的Datasheet PDF文件第13页浏览型号MT90826AG的Datasheet PDF文件第14页浏览型号MT90826AG的Datasheet PDF文件第15页浏览型号MT90826AG的Datasheet PDF文件第16页  
MT90826  
Data Sheet  
Pin Description (continued)  
Pin # MQFP  
Pin # PBGA  
Pin # LBGA  
Name  
Description  
148 - 153  
154,155  
158  
G3,J1,H3,J2,J3,K1, H3,H1,H2,J1,J3,K1  
D0 - 5,  
D6, D7  
D8  
D9 - 13  
D14, D15  
Data Bus 0 to 15 (5 V Tolerant I/O).  
These pins form the 16-bit data bus of  
the microprocessor port.  
K2,K3  
L1  
L1,J2  
L2  
3 - 7  
L2,M1,M2,M3,N1,  
N2,N3  
L3,M1,K3,M2,K4  
M3,K2  
8,9  
10  
M4  
M4  
DTA  
Data Transfer Acknowledgment  
(Three-state Output). This output  
pulses low from tristate to indicate that  
a databus transfer is complete. A pull-  
up resistor is required to hold a HIGH  
level when the pin is tristated.  
15  
14  
13  
N5  
N4  
M5  
J5  
L4  
K5  
DS  
R/W  
CS  
Data Strobe (5 V Tolerant Input). This  
active low input works in conjunction  
with CS to enable the read and write  
operations.  
Read/Write (5 V Tolerant Input). This  
input controls the direction of the data  
bus lines (D0-D15) during a  
microprocessor access.  
Chip Select (5 V Tolerant Input).  
Active low input used by a  
microprocessor to activate the  
microprocessor port.  
16 - 20  
23 - 31  
M6,N6,N7,M7,N8  
N9,N10,M8,M9,L7  
L8,M10,L9,L10  
M5,L6,K6,M6,L7,  
K7,M7,M8,K8,K9,  
L8,M9,L9,L5  
A0 - A4  
Address 0 to 13 (5 V Tolerant Input).  
These lines provide the A0 - A13  
address lines when accessing the  
internal registers or memories.  
A5 - A13  
1,2,39,40,41,48, E3,F3,H11,J11,  
J9,J10  
NC  
No Connect. These pins have to be  
49,80,81,120,  
121,159,160  
J12,K8,K11,  
L3,L4,L5,L6.  
left unconnected.  
1.0 Device Overview  
The MT90826 Quad Digital Switch is capable of switching up to 4,096 × 4,096 channels. The MT90826 is designed  
to switch 64 Kbps PCM or N x 64 Kbps data. The device maintains frame integrity in data applications and minimum  
throughput delay for voice applications on a per channel basis.  
The serial input streams of the MT90826 can have a bit rate of 2.048, 4.096, 8.192 or 16.384 Mbps and are  
arranged in 125 µs wide frames, which contain 32, 64,128 or 256 channels, respectively. The data rates on input  
and output streams match. All inputs and outputs may be programmed to 2.048, 4.096 or 8.192 Mbps. STi0-15 and  
STo0-15 may be set to 16.384 Mbps. Combinations of two bit rates, N and 2N are provided. See Table 1.  
By using Zarlink’s message mode capability, the microprocessor can access input and output timeslots on a per  
channel basis. This feature is useful for transferring control and status information for external circuits or other ST-  
BUS devices.  
To correct for backplane delays, the MT90826 has a frame offset calibration function which allows users to measure  
the frame delay on any of the input streams, This information can then be used to program the input offset dealy for  
each individual stream. Refer to Table 7, 8, and 9 and Figure 6. In addition, the MT90826 allow users to advance  
12  
Zarlink Semiconductor Inc.