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MT90826AG 参数 Datasheet PDF下载

MT90826AG图片预览
型号: MT90826AG
PDF下载: 下载PDF文件 查看货源
内容描述: 四数字开关 [Quad Digital Switch]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 46 页 / 571 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT90826  
Data Sheet  
Pin Description (continued)  
Pin # MQFP  
Pin # PBGA  
Pin # LBGA  
Name  
Description  
44  
L12  
L12  
K12  
J11  
IC2  
Internal Connection 2 (3.3 V Input  
with internal pull-down). Connect to  
VSS for normal operation.  
46  
47  
L13  
K12  
IC3  
F0i  
Internal Connection 3 (3.3 V Input  
with internal pull-down). Connect to  
VSS for normal operation.  
Master Frame Pulse (5 V Tolerant  
Input). This input accepts a 122 ns or  
60 ns wide negative frame pulse. The  
CPLL bit in the control register  
determines the usage of the frame  
pulse width. See Table 6 for details.  
50  
51  
K10  
K9  
H9  
G9  
PLLGND  
PLLVDD  
Phase Lock Loop Ground.  
Phase Lock Loop Power Supply.  
3.3 V  
52  
K13  
J12  
CLK  
Master Clock (5 V Tolerant Input).  
Serial clock for shifting data in/out on  
the serial streams. This pin accepts a  
clock frequency of 8.192 MHz or  
16.384 MHz. The CPLL bit in the  
control register determines the usage  
of the clock frequency. See Table 6 for  
details.  
55  
J13  
H10  
ODE  
Output Drive Enable (5 V Tolerant  
Input). This is the output-enable  
control pin for the STo0 to STo31 serial  
outputs. See Table 2 for details.  
56  
57  
H13  
H12  
H11  
H12  
STi0/FEi0,  
STi1/FEi1  
Serial Input Streams 0 to 31 and  
Frame Evaluation Inputs 0 to 31 (5 V  
Tolerant Inputs). Serial data input  
streams. These streams may have  
data rates of 2.048, 4.096, 8.192 or  
16.384 Mbps, depending upon the  
value programmed at bits DR0 - DR2 in  
the control register. In the frame  
evaluation mode, they are used as the  
frame evaluation inputs.  
58  
G13  
G12  
STi2/FEi2  
59  
G12  
G11  
STi3/FEi3  
67-70  
78,79  
82,83  
91-94  
102-105  
113-116  
126-129  
137-140  
F13,F12,E13,E12  
B13,A13  
F11,F12,E12,E11  
B12,A12  
STi4-7/FEi4-7  
STi8-9/FEi8-9  
A12,B12  
B11,A11  
STi10-11/FEi10-11  
STi12-15/FEi12-15  
STi16-19/FEi16-19  
STi20-23/FEi20-23  
STi24-27/FEi24-27  
STi28-31/FEi28-31  
C11,C10,C9,C8  
A7,B7,A6,B6  
A5,B5,A4,B4  
A2,B2,A1,B1  
E2,F2,E1,F1  
C10,C9,C8,D8  
A6,A5,B6,B5,  
A4,A3,B4,B3  
D2,C2,C1,D1  
E2,E1,F1,F2  
61-64  
72-75  
G11,F11,E11,D11  
D13,C13,D12,C12  
A11,B11,A10,B10  
B9,A9,B8,A8  
C7,C6,C5,C4  
A3,B3  
G10,F10,D10,E10  
D12,C12,D11,C11  
B10,A10,B9,A9  
B8,A8,A7,B7  
C7,C6,C5,C4  
A2,B2  
STo0 - 3  
STo4 - 7  
ST-BUS Output 0 to 31 (Three-state  
Outputs). Serial data output streams.  
These streams may have data rates of  
2.048, 4.096, 8.192, or 16.384 Mbps,  
depending upon the value programmed  
at bits DR0 - DR2 in the control  
register.  
85-88  
STo8 - 11  
96-99  
STo12 - 15  
STo16 - 19  
STo20, STo21  
STo22, STo23  
STo24 - 27  
STo28 - 31  
107-110  
118,119  
122,123  
131-134  
142-145  
D3,C3  
B1,A1  
D2,C2,C1,D1  
G1,G2,H1,H2  
C3,D3,E4,E3  
F3,G3,G1,G2  
11  
Zarlink Semiconductor Inc.