Secondary Registers for Test and De-Bugging MT312
10.2 Secondary Registers for Test and De-Bugging Read/Write Registers
10.2.1 AGC Initial Value. Register 40 (R/W)
AGC INIT (40)
Default value
Front End AGC initial value.
59 dec.
255 dec.
0 dec.
3B hex.
FF hex.
00 hex.
0A hex.
1E hex.
AGC INIT[7:0]
10.2.2 AGC Maximum Value. Register 42 (R/W)
AGC MAX (42)
Default value
Front End AGC maximum value.
AGC MAX[7:0]
10.2.3 AGC Minimum Value. Register 43 (R/W)
AGC MIN (43)
Default value
Front End AGC minimum value.
AGC MIN[7:0]
10.2.4 AGC Lock Threshold Value. Register 44 (R/W)
AGC LK TH (44) Default value
10 dec.
AGC LK TH[7:0] Front End AGC lock threshold value.
10.2.5 AGC Lock Threshold Value. Register 45 (R/W)
TS AGC LK TH (45)
Default value
30 dec.
TS AGC LK
TH[7:0]
Timing synchroniser fine AGC lock threshold value.
10.2.6 AGC Power Setting Initial Value. Register 46 (R/W)
AGC PWR SET (46) Default value
AGC power setting initial value.
20 dec.
14 hex.
AGC PWR
SET[7:0]
10.2.7 QPSK Miscellaneous. Register 47 (R/W)
QPSK MISC (47)
Default value
Reserved, must be set low,
0 dec.
00 hex.
QPSK
MISC[B7-0]
63
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