Le58083
Data Sheet
Signaling and Control (SC) Channel
The upstream and downstream SC channels are continuously carrying I/O information every frame to and from the Le58083
Octal SLAC device in the C/I field. This allows the upstream processor to have immediate access to the output (downstream) and
input (upstream) data present on the Le58083 Octal SLAC device’s programmable I/O port.
The MR and MX bits are used for handshaking during data exchanges on the monitor channel.
Downstream C/I Channel
The Le58083 Octal SLAC device receives the MSBs first.
<---------------- Downstream SC Octet ------------------>
MSB
7
LSB
0
6
5
4
3
2
1
C7
C6
C5
C4
C3
A
MR
MX
C
C
C
C
C
|<------------------- C/I Field ------------------->|
A: Channel Address Bit
0: Selects CH 1 or 3 as the downstream data destination
1: Selects CH 2 or 4 as the downstream data destination
C7C–C3C: SLIC device output latch bits 7–3 of the channel selected by A.
C = 1 or 2, the channel selected by A
If the Le58083 Octal SLAC device’s programmable I/O ports, CD1, CD2, and C3 are programmed for Input mode, then data is
obtained through the Upstream C/I channel.
Figure 27 shows the transmission protocol for the downstream C/I. Whenever the received pattern of C/I bits 6–1 is different from
the pattern currently in the C/I input register, the new pattern is loaded into a secondary C/I register and a latch is set. When the
next pattern is received (in the following frame) while the latch is set, the following rules apply:
1. If the received pattern corresponds to the pattern in the secondary register, the new pattern is loaded into the C/I register for
the addressed channel and the latch is reset. The updated C/I register data appears at the programmable I/O pins of the
device one frame (125 µs) later if they are programmed as outputs.
2. If the received pattern is different from the pattern in the secondary register and different from the pattern currently in the C/
I register, the newly received pattern is loaded into the secondary C/I register and the latch remains set. The data at the PI/
O port remains unchanged.
3. If the received pattern is the same as the pattern currently in the C/I register, the C/I register is unchanged and the latch is
reset.
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