Le58083
Data Sheet
E8/E9h Write/Read Ground Key Filter
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
1
1
1
0
1
0
0
R/W
GK0
RSVD
RSVD
RSVD
RSVD
GK3
GK2
GK1
Filter Ground Key
GK = 0–15
Filter sampling period in 1 ms
GK contains the filter sampling time (in ms) of the CD1B data (usually Ground Key) or CD2 entering the Real Time Data register
described earlier. A value of 0 disables the Ground Key filter for that particular channel.
Power Up and Hardware Reset (RST) Value = x0h.
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
GENERAL CIRCUIT INTERFACE (GCI) SPECIFICATIONS
GCI General Description
When the CS/PG_1 and CS/PG_2 device pins are connected to DGND and DCLK/S0_1and DCLK/S0_2 are static (not toggling),
GCI operation is selected. The Le58083 Octal SLAC device conforms to the GCI standard where data for eight GCI channels are
combined into one serial bit stream. A GCI channel contains the control and voice data for two analog channels of the Octal SLAC
device. Four GCI channels are required to access all eight channels of the Le58083 Octal SLAC device. The Le58083 Octal
SLAC device sends Data Upstream out of the DU pin and receives Downstream Data on the DD pin. Data clock rate and frame
synchronization information goes to the Le58083 Octal SLAC device on the DCL (Data Clock) and FSC input pins, respectively.
Two of eight GCI channels are selected by connecting the S0 and S1 channel selection pins on the Le58083 Octal SLAC device
to DGND or VCCD as shown in Table Table 8. As an example, doing GCI operation selection if DCLK/S0_1, DIO/S1_1, and DIO/
S1_2 were tied to DGND and DCLK/S0_2 was tied to VCCD, then the internal four-channel SLAC 1 device would communicate
on GCI channels 0 & 1 and internal SLAC 2 would communicate on GCI channels 2 and 3.
Table 8. GCI Channel Assignment Codes
S1
S0
GCI Channels #
0 & 1
DGND
DGND
VCCD
VCCD
DGND
VCCD
DGND
VCCD
2 & 3
4 & 5
6 & 7
In the time slot control block (shown in Figure 25), the Frame Sync (FSC) pulse identifies the beginning of the Transmit and
Receive frames and all GCI channels are referenced to it. Voice (B1 and B2), C/I, and monitor data are sent to the Upstream
Multiplexer where they are combined and serially shifted out of the DU pin during the selected GCI Channels. The Downstream
Demultiplexer uses the same channel control block information to demultiplex the incoming GCI channels into separate voice
(B1 and B2), C/I, and monitor data bytes.
The Le58083 Octal SLAC device supports an eight GCI channel bus (16 analog channels). The external clock applied to the DCL
pin is either 2.048 MHz or 4.096 MHz. The Le58083 Octal SLAC device determines the incoming clock frequency and adjusts
internal timing automatically to accommodate single or double clock rates.
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
