Le58083
Data Sheet
44/45h Write/Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
0
0
1
0
R/W
TAB
XE
RCS2
RCS1
RCS0
TCS2
TCS1
TCS0
Transmit on A and B
TAB = 0*
TAB = 1
Transmit data on highway selected by TPCM (see Commands 40/41h).
Transmit data on both highways A and B
Transmit Edge (Global parameter) - Program the same in both four channel groups
XE = 0*
XE = 1
Transmit changes on negative edge of PCLK
Transmit changes on positive edge of PCLK
Receive Clock Slot (Global parameter) - Program the same in both four channel groups
RCS = 0*–7 Receive Clock Slot number
Transmit Clock Slot (Global parameter) - Program the same in both four channel groups
TCS = 0*–7
Transmit Clock Slot number
The XE bit and the clock slots apply to all four channels; however, they cannot be written or read unless at least one channel is
selected in the Channel Enable Register; however, TAB is channel specific.
* Power Up and Hardware Reset (RST) Value = 00h.
46/47h Write/Read Chip Configuration Register
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
0
0
1
1
R/W
INTM
CHP
SMODE
CMODE
CSEL3
CSEL2
CSEL1
CSEL0
Interrupt Mode (Global parameter)
INTM = 0
TTL-compatible output
Open drain output
INTM = 1*
Chopper Clock Control (Global parameter)
CHP = 0*
CHP = 1
Chopper Clock is 256 kHz (2048/8 kHz)
Chopper Clock is 292.57 kHz (2048/7 kHz)
PCM Signaling Mode (Global parameter) - Program the same in both four channel groups
SMODE = 0*
SMODE = 1
No signaling on PCM highway
Signaling on PCM highway
Clock Source Mode (Global parameter) - Program the same in both four channel groups
CMODE = 0
CMODE = 1*
MCLK used as master clock; no E1 multiplexing allowed
PCLK used as master clock; E1 multiplexing allowed if enabled in Command C8/C9h.
The master clock frequency can be selected by CSEL. The master clock frequency selection affects all channels.
Master Clock Frequency (Global parameter) - Program the same in both four channel groups
CSEL = 0000
CSEL = 0001
CSEL = 0010
CSEL = 0011
CSEL = 01xx
CSEL = 10xx
CSEL = 11xx
CSEL = 1010*
1.536 MHz
1.544 MHz
2.048 MHz
Reserved
Two times frequency specified above (2 x 1.536 MHz, 2 x 1.544 MHz, or 2 x 2.048 MHz)
Four times frequency specified above (4 x 1.536 MHz, 4 x 1.544 MHz, or 4 x 2.048 MHz)
Reserved
8.192 MHz is the default
48
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
