Le58083
Data Sheet
Commands are provided to read values from the following channel monitors:
Table 5. Channel Monitors
Monitor
CD1–C5
CD1B
Description
Read SLIC device Inputs
Multiplexed SLIC device Input
Transmit PCM data
MPI
53h
53h
CDh
GCI
SOP 10
SOP 10
—
XDAT
Commands are provided to assign values to the following global (four-channel group) chip parameters. Parameters marked with
an asterisk (*) must be programmed the same in both four-channel groups.
Table 6. Global Chip Parameters
Parameter
XE
RCS
TCS
INTM
CHP
Description
Transmit PCM Clock Edge
Receive Clock Slot
MPI
GCI
—
—
*
*
*
44/45h
44/45h
44/45h
46/47h
46/47h
C8/C9h
46/47h
46/47h
46/47h
4A/4Bh
4A/4Bh
4A/4Bh
C8/C9h
C8/C9h
C8/C9h
C8/C9h
6C/6Dh
Transmit Clock Slot
—
Interrupt Output Drive Mode
Chopper Clock Frequency
Enable Chopper Clock Output
Select Signaling on the PCM Highway
Select Master Clock Mode
Select Master Clock Frequency
Robbed Bit Enable
SOP 6
SOP 6
SOP 11
—
—
—
—
SOP 9
—
SOP 11
SOP 11
SOP 11
—
ECH
*
*
*
SMODE
CMODE
CSEL
RBE
VMODE
EC
DSH
EE1
E1P
DPCK
MCDxC
VOUT Mode
Channel Enable Register
Debounce Time for CD1
Enable E1 Output
E1 Polarity
Double PCLK Operation
Interrupt Mask Register
*
SOP 14
Commands are provided to read values from the following global four-channel group chip status monitors:
Table 7. Global Chip Status Monitors
Monitor
CDxC
Description
Real Time Data Register
MPI
4D/4Fh
54/55h
73h
—
—
GCI
SOP 13, C/I
SOP 8
TOP 1
CIC
CFAIL
RCN
CONF
DT
Clock Failure Bit
Revision Code Number
Configuration (0000)
Device Type (10)
CIC
Microprocessor Interface Description
When PCM/MPI mode is selected via the CS/PG and DCLK/S0 pins, a microprocessor can be used to program the Le58083
Octal SLAC device and control its operation using the Microprocessor Interface (MPI). Data programmed previously can be read
out for verification.
The following description of the MPI (Microprocessor Interface) for a four-channel group is valid for channels 1– 4. If desired,
multiple channels can be programmed simultaneously with identical information by setting multiple Channel Enable bits. Channel
enables are contained in the Channel Enable register and are written or read using Command 4A/4Bh. If multiple Channel Enable
bits are set for a read operation, only data from the first enabled channel will be read.
The MPI physically consists of a serial data input/output (DIO), a data clock (DCLK), and a chip select (CS). Individual Channel
Enable bits EC1, EC2, EC3, and EC4 are stored internally in the Channel Enable register of the Le58083 Octal SLAC device.
The serial input consists of 8-bit commands that can be followed with additional bytes of input data, or can be followed by the
Le58083 Octal SLAC device sending out bytes of data. All data input and output is MSB (D7) first and LSB (D0) last. All data
bytes are read or written one at a time, with CS going High for at least a minimum off period before the next byte is read or written.
Only a single channel should be enabled during read commands.
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
