Le58083
Data Sheet
52/53h Write/Read SLIC Device Input/Output Register
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
1
0
0
1
R/W
CD1
C7
C6
CD1B
C5
C4
C3
CD2
Pins CD1, CD2, and C3 through C7 are set to 1 or 0. The data appears latched on the CD1, CD2, and C3 through C5 SLIC I/O
pins, provided they were set in the Output mode (see Command 54/55h). The data sent to any of the pins set to the
Input mode is latched, but does not appear at the pins. The CD1B bit is only valid if the E1 Multiplex mode is enabled (EE1 = 1).
C7 and C6 are outputs only.
* Power Up and Hardware Reset (RST) Value = 00h
54/55h Write/Read SLIC Device Input/Output Direction, Read Status Bits
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
Input Data
0
1
0
1
0
1
0
R/W
RSVD
CSTAT
CFAIL
IOD5
IOD4
IOD3
IOD2
IOD1
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Channel Status (Read status only, write as 0)
CSTAT = 0
CSTAT = 1
Channel is inactive (Standby state).
Channel is active.
Clock Fail (Read status only, write as 0) (Global status bit)
CFAIL* = 0
CFAIL = 1
The internal clock is synchronized to frame synch.
The internal clock is not synchronized to frame synch.
* The CFAIL bit is independent of the Channel Enable Register.
I/O Direction (Read/Write)
IOD5 = 0*
C5 is an input
C5 is an output
C4 is an input
C4 is an output
C3 is an input
C3 is an output
CD2 is an input
CD2 is an output
CD1 is an input
CD1 is an output
IOD5 = 1
IOD4 = 0*
IOD4 = 1
IOD3 = 0*
IOD3 = 1
IOD2 = 0*
IOD2 = 1
IOD1 = 0*
IOD1 = 1
Pins CD1, CD2, and C3 through C5 are set to Input or Output modes individually.
* Power Up and Hardware Reset (RST) Value = 00h
51
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
