Le58083
Data Sheet
All commands that require additional input data to the device must have the input data as the next N words written into the device
(for example, framed by the next N transitions of CS). All unused bits must be programmed as 0 to ensure compatibility with future
parts. All commands that are followed by output data will cause the device to output data for the next N transitions of CS going
Low. The Le58083 Octal SLAC device will not accept any commands until all the data has been shifted out. The output values
of unused bits are not specified.
An MPI cycle is defined by transitions of CS and DCLK. If the CS lines are held in the High state between accesses, the DCLK
may run continuously with no change to the internal control data. Using this method, the same DCLK can be run to a number of
Le58083 Octal SLAC devices, and the individual CS lines will select the appropriate device to access. Between command
sequences, DCLK can stay in the High state indefinitely with no loss of internal control information regardless of any transitions
on the CS lines. Between bytes of a multibyte read or write command sequence, DCLK can also stay in the High state indefinitely.
DCLK can stay in the Low state indefinitely with no loss of internal control information, provided the CS lines remain at a High
level.
If a low period of CS contains less than 8 positive DCLK transitions, it is ignored. If it contains 8 to 15 positive transitions, only
the last 8 transitions matter. If it contains 16 or more positive transitions, a hardware reset in the part occurs. If the chip is in the
middle of a read sequence when CS goes Low, data will be present at the DIO pin even if DCLK has no activity. If CS is held low
for two or more cycles of Frame Sync (FS) and DCLK is static (no toggling), then the Le58083 Octal SLAC device switches to
the General Circuit Interface mode of operation.
SUMMARY OF MPI COMMANDS
Hex*
00h
Description
Deactivate (Standby state)
Software Reset
02h
04h
06h
Hardware Reset
No Operation
0Eh
Activate (Operational state)
40/41h
42/43h
44/45h
46/47h
4A/4Bh
4Dh
Write/Read Transmit Time Slot and PCM Highway Selection
Write/Read Receive Time Slot and PCM Highway Selection
Write/Read REC & TX Clock Slot and TX Edge
Write/Read Configuration Register
Write/Read Channel Enable & Operating Mode Register
Read Real Time Data Register
4Fh
Read Real Time Data Register and Clear Interrupt
Write/Read AISN and Analog Gains
Write/Read SLIC device Input/Output Register
Write/Read SLIC device Input/Output Direction and Status Bits
Write/Read Operating Functions
Write/Read Interrupt Mask Register
Write/Read Operating Conditions
50/51h
52/53h
54,55h
60/61h
6C/6Dh
70/71h
73h
Read Revision Code Number (RCN)
80/81h
82/83h
84/85h
86/87h
88/89h
8A/8Bh
96/97h
98/99h
9A/9Bh
C8/C9h
CDh
Write/Read GX Filter Coefficients
Write/Read GR Filter Coefficients
Write/Read Z Filter Coefficients (FIR and IIR)
Write/Read B1 Filter Coefficients (FIR)
Write/Read X Filter Coefficients
Write/Read R Filter Coefficients
Write/Read B2 Filter Coefficients (IIR)
Write/Read Z Filter Coefficients (FIR only)
Write/Read Z Filter Coefficients (IIR only)
Write/Read Debounce Time Register
Read Transmit PCM Data
Write/Read Ground Key Filter Sampling Interval
E8/E9h
Note:
*All codes not listed are reserved by Zarlink and should not be used.
45
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
