Le58083
Data Sheet
Figure 20. SLIC Device I/O, E1 Multiplex and Real-Time Data Register Operation
SLIC device Input Register
MPI Command 53h
or GCI Upstream
SC Channel Data
C7 C6 CD1B C5 C4
C3 CD2 CD1
D
Q
EN/HOLD
*
CD1
CD2
C3
C4
C5
C6
C7
D
Q
EN/HOLD
I/O Direction
Register
1
0
*
MUX
MPI Command
Output Latch
LD Enable
GK Enable
54/55h or GCI
Command SOP 8
SLIC Output
Register
MPI Command 52h
or GCI Downstream
SC Channel Data
Ground Key Filter (time set
via
MPI Command E8/E9h or
Debounce Time
(Channel 1
Shown)
(set via MPI Command C8/C9h or
GCI Command SOP 11)
EE1 Bit
E1 Source
(Internal)
Same for
Channels
2, 3, 4
{
Delay
(See Figure 21
for details)
MCLK/E1
Real Time Data Register
(MPI Command 4D/4Fh
or GCI UpstreamSC Channel data)
E1P
CDB CDA CDB CDA CDB CDA CDB CDA
1
4
4
3
3
2
2
1
INT
Interrupt Mask Register
(MPI Command 6C/6Dh
or GCI Command SOP 14)
(MPI Command 70/71h
ATI
or GCI Command SOP 5)
MCDB MCDA MCDB MCDA MCDB MCDA MCDB MCDA
1
4
4
3
3
2
2
1
Note:
* Transparent latches: When enable input is high, Q output follows D input. When enable input goes low, Q output is latched at last state.
34
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
