Le58083
Data Sheet
Figure 22. MPI Real-Time Data Register
CD1
CDA
D
Q
Debounce Counter
DSH0 – DSH3
D
Q
D
Q
D
Q
EN/HOLD
*
Debounce Period
(0 – 15 ms)
Q
CK
RST
8
FS (8 kHz)
a. Loop Detect Debounce Filter
Notes:
*Transparent latch: Output follows input when EN is high; output holds last state when EN is low.
Debounce counter: Output is high after counting to programmed (DSH) number of 1 ms clocks; counter is reset for CD1 input changes at 125 µs
sample period. DSH0 - DSH3 programmed value is common for all four channels, but debounce counter is separate per channel.
MUX
CD2 or CD1B
GK
=
=
0
0
CDB
UP/DN
Q
GK0 – GK3
Ground-Key
Sampling Interval
1 – 15 ms
GK
GK
Six-State
Up/Down
Counter
RST
1 kHz
Clock Divider
(1 – 15 ms
clock output)
b. Ground-Key Filter
Notes:
Programmed value of GK0 - GK3 determines clock rate (1 - 15 ms) of six-state counter.
If GK value = 0, the counter is bypassed and no buffering occurs.
Six-state up/down counter: Counts up when input is high; counts down when input is low.
Output goes and stays high when maximum count is reached; output goes and stays low when count is down to zero.
Real-Time Data Register Operation
To obtain time-critical data such as off/on-hook and ring trip information from the SLIC device with a minimum of processor time
and effort, the Le58083 Octal SLAC device contains two 8-bit Real Time Data registers. These registers each contain CDA and
CDB bits from four channels. The CDA bit for each channel is a debounced version of the CD1 input. The CDA bit is normally
used for hook switch. The CDB bit for each channel normally contains the debounced value of the CD2 input bit; however, if the
E1 multiplex operation is enabled, the CDB bit will contain the debounced value of the CD1B bit. CD1 and CD2 can be assigned
to off-hook, ring trip, ground key signals, or other signals. Frame sync is needed for the debounce and the ground-key signals. If
Frame sync is not provided, the real-time register will not work. The register is read using MPI Command 4D/4Fh, GCI Command
SOP 13, and may be read at any time regardless of the state of the Channel Enable Register. This allows off/on-hook, ring trip,
or ground key information for four channels to be obtained from the Le58083 Octal SLAC device with one read operation versus
one read per channel. If these data bits are not used for supervision information, they can be accessed on an individual channel
basis in the same way as C3–C5; however, CD1 and CD1B will not be debounced. This Real-Time Data register is available in
both MPI and GCI modes. In the GCI mode, this real-time data is also available in the field of the upstream SC octet.
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