Le58083
Data Sheet
Interrupt
In addition to the Real Time Data registers, interrupt signals have been implemented in the Le58083 Octal SLAC device. An
interrupt signal is an Active Low output signal which pulls Low whenever the unmasked CD bits change state (Low to High or
High to Low); or whenever the transmit PCM data changes on a channel in which the Arm Transmit Interrupt (ATI) bit is on. The
interrupt control is shown in Figure 20. The interrupt remains Low until the appropriate register is read. This output can be
programmed as TTL or open drain output by the INTM bit, MPI Command 46/47h or GCI Command SOP 6. When an interrupt
is generated, all of the unmasked bits in the Real Time Data register latch and remain latched until the interrupt is cleared. The
interrupt is cleared by reading the register with MPI Command 4Fh or GCI Command SOP 13, by writing to the interrupt mask
register (MPI Command 6Ch, GCI Command SOP 14), or by a reset. If any of the inputs to the unmasked bits in the Real Time
Data register are different from the register bits when the interrupt is cleared by reading the register, a new interrupt is immediately
generated with the new data latched into the Real Time Data register. For this reason, the interrupt logic in the controller should
be level-sensitive rather than edge-sensitive.
Interrupt Mask Register
The Real Time Data register data bits can be masked from causing an interrupt to the processor using the interrupt mask register.
The contents of the mask register can be written or read via the MPI Command 6C/6Dh, GCI Command SOP 14.
Active State
Each channel of the Le58083 Octal SLAC device can operate in either the Active (Operational) or Inactive (Standby) state. In the
Active state, individual channels of the Le58083 Octal SLAC device can transmit and receive PCM or linear data and analog
information. The Active state is required when a telephone call is in progress. The activate command (MPI Command 0Eh, GCI
Command SOP 4) puts the selected channels (see channel enable register for PCM/MPI Mode) into this state (CSTAT = 1).
Bringing a channel of the Le58083 Octal SLAC device into the Active state is only possible through the MPI command or the GCI
command.
Inactive State
All channels of the Le58083 Octal SLAC device are forced into the Inactive (Standby) state by a power-up or hardware reset.
Individual channels can be programmed into this state (CSTAT = 0) by the deactivate command (MPI Command 00h, GCI
Command SOP 1) or by the software reset command (MPI Command 02h, GCI Command SOP 2). Power is disconnected from
all nonessential circuitry, while the MPI remains active to receive commands. The analog output is tied to VREF through a resistor
whose value depends on the VMODE bit. All circuits that contain programmed information retain their data in the Inactive state.
Chopper Clock
The Le58083 Octal SLAC device provides chopper clock outputs to drive the switching regulators on some Zarlink SLIC
devices. The clock frequency is selectable as 256 or 292.57 kHz by the CHP bit (MPI Command 46/47h, GCI Command SOP
6). The duty cycle is given in the Switching Characteristics section. The chopper output must be turned on with the ECH bit (MPI
Command C8/C9h, GCI Command SOP 11).
Reset States
The Le58083 Octal SLAC device can be reset by application of power, by an active Low on the hardware Reset pin (RST), by a
hardware reset command, or by CS_1 or CS_2 Low for 16 or more rising edges of DCLK (resets the internal four-channel SLAC
selected only). This resets the Le58083 Octal SLAC device to the following state:
1. A-law companding is selected.
2. Default B, X, R, and Z filter values from ROM are selected and the AISN is set to zero.
3. Default digital gain blocks (GX and GR) from ROM are selected. The analog gains, AX and AR, are set to 0 dB and the input
attenuator is turned on (DGIN = 0).
4. The previously programmed B, Z, X, R, GX, and GR filters in RAM are unchanged.
5. SLIC device input/outputs CD1, CD2, C3, C4, and C5 are set to the Input mode.
6. All of the test states in the Operating Conditions register are turned off (0s).
7. All four channels are placed in the Inactive (Standby) mode.
8. For PCM/MPI mode, transmit time slots and receive time slots are set to 0, 1, 2, and 3 for channels 1, 2, 3, and 4, respectively.
The clock slots are set to 0, with transmit on the negative edge. For GCI mode, operation is determined by S0 and S1.
9. DXA/DU port is selected for all channels.
10. DRA/DD port is selected for all channels.
11. The master clock frequency in PCM/MPI mode is selected to be 8.192 MHz and is programmed to come from PCLK. In GCI
mode, DCL is 2.048 or 4.096 MHz and is determined by the Le58083 Octal SLAC device.
12. All four channels are selected in the Channel Enable Register for PCM/MPI mode.
13. Any pending interrupts are cleared, all interrupts are masked, and the Interrupt Output state is set to open drain.
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Zarlink Semiconductor Inc.
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