Le58083
Data Sheet
OPERATING THE LE58083 OCTAL SLAC DEVICE
The following sections describe the operation of the Le58083 Octal SLAC device. The description is valid for all eight channels;
consequently the subscripts have been dropped. For example, VOUT refers to either VOUT1_1, VOUT1_2, etc.
The command addresses are the same for both of the internal four-channel groups. Therefore, chip select one (CS_1) controls
the first four channel group and chip select two (CS_2) controls the second four-channel group.
Power-Up Sequence
The recommended Le58083 Octal SLAC device power-up sequence is to apply:
1. Analog and digital ground
2. VCC, signal connections, and Low on RST (refer to the switching characteristics section for timing specifications of RST)
3. High on RST
The software initialization recommended for each internal four-channel group includes:
1. Wait 1 ms. after Reset.
2. For PCM/MPI mode, select master clock frequency and source (Command 46/47h). This should turn off the CFAIL bit
(Command 55h) within 400 µs.
In GCI mode, DCL is the clock source. The CFAIL bit (GCI Command SOP 8) is set to 1 until the device has determined and
synchronized to the DCL frequency, 4.096 MHz or 2.048 MHz. If channels are activated while CFAIL is a 1, no device
damage will occur, but high audible noise may appear on the line. Also, the CD1, CD2, and C3 - C7 bits may not be stable.
3. Program filter coefficients and other parameters as required.
4. Activate (MPI Command 0Eh, GCI Command SOP 4).
If the power supply (VCCD) falls below an internal threshold, the device is reset and will require complete reprogramming with
the above sequence. A reset may be initiated by connection of a logic Low to the RST pin. A reset will also be generated on a
selected internal four-channel SLAC device when chip select _1(CS/PG_1) or chip select _2 or both chip selects are held low for
16 rising edges of DCLK when chip selects returns high. The RST pin may be tied to VCCD if it is not used in the system.
PCM and GCI State Selection
The Le58083 Octal SLAC device can switch between PCM/MPI and GCI modes. Table Table 3 lists the selection requirements.
Table 3. PCM/GCI Mode Selection
From State
To State
Requirement
Power On or
Hardware
Reset
CS_1 and CS_2 = 1 or
DCLK_1 and DCLK_2 have
ac clock present
PCM
Power On or
Hardware
Reset
CS_1 and CS_2 = 0 and
DCLK_1 and DCLK_2 do
not have ac clock present
GCI
CS_1 and CS_2 = 1 or
DCLK_1 and DCLK_2 have
ac clock present
GCI
PCM
No commands yet sent in
PCM state andCS_1 and
CS_2 = 0 (for more than 2
FS) and DCLK_1 and
DCLK_2 do not have ac
clock present
PCM
GCI
Power On or
Hardware
Reset
Power On or
Hardware
Reset
Commands have been sent
in PCM state and Hardware
Reset generated
PCM
GCI
Not allowed
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