Le58083
Data Sheet
Channel Enable (EC) Register (PCM/MPI Mode)
In PCM/MPI mode, a channel enable (EC) register has been implemented in each four-channel group of the Le58083 Octal SLAC
device in order to reduce the effort required to address individual or multiple channels of the Le58083 Octal SLAC device. The
register is written using MPI Command 4A/4Bh. Each bit of the register is assigned to one unique channel, bit 0 for channel 1,
bit 1 for channel 2, bit 2 for channel 3, and bit 3 for channel 4. The channel or channels are enabled when their corresponding
enable bits are High. All enabled channels receive the data written to the Le58083 Octal SLAC device. Since, the Le58083 Octal
SLAC device consist of two four-channel SLAC devices both chip selects need to be enabled, along with all the channel enable
bits, to program all eight channels. This enables a Broadcast mode (all channels enabled) to be implemented simply and
efficiently, and multiple channel addressing is accomplished without increasing the number of I/O pins on the device. The
Broadcast mode can be further enhanced by providing the ability to select many chips at once; however, care must be taken not
to enable more than one chip in the Read state. This can lead to an internal bus contention, where excess power is dissipated.
(Bus contention will not damage the device.)
In GCI mode, the individual channels are controlled by their respective Monitor and SC channels embedded in the GCI channels
selected by the device (S0, S1).
SLIC Device Control and Data Lines
The Le58083 Octal SLAC device has five SLIC device programmable digital input/output pins per channel (CD1–C5). Each of
these pins can be programmed as either an input or an output using the I/O Direction register (MPI Command 54/55h, GCI
Command SOP 8). Also, there are the two additional output only pins per channel, C6-C7 (see Figure 20). The output latches
can be written with MPI Command 52h or through the CI1 to CI5 bits present in the downstream SC channel; however, only those
bits programmed as outputs will actually drive the pins. The inputs can be read with MPI Command 53h, GCI Command SOP 10
or on the Upstream CI bits, in the SC channel. If a pin is programmed as an output, the data read from it will be the contents of
the output latch. In GCI mode, this data can be read using GCI Command SOP 10, but the output bits are not sent upstream in
the SC channel. It is recommended that any of the SLIC device input/output control and data pins, which are to be programmed
as outputs, be written to their desired state before writing the data which configures them as outputs with the I/O direction register
MPI Command 54/55h, GCI Command SOP 8. This ensures that when the output is activated, it is already in the correct state,
and will prevent unwanted data from being driven from the SLIC device output pins. It is possible to make a SLIC device control
output pull up to a non-standard voltage (V < 5.25 V) by connecting a resistor from the output to the desired voltage, sending zero
to the output, and using the DIO bit to tri-state the output.
Clock Mode Operation
The Le58083 Octal SLAC device operates with multiple clock signals. The master clock is used for internal timing including
operation of the digital signal processing. In PCM/MPI mode, the master clock may be derived from either the MCLK or PCLK
source. When MCLK is used as the master clock, it should be synchronous to FS. In GCI mode, the master clock is obtained
from the DCL clock only. The allowed frequencies are listed under Command 46/47h for PCM/MPI mode. In GCI mode, DCL can
be only 2.048 MHz or 4.096 MHz.
In PCM/MPI mode, the PCM clock (PCLK) is used for PCM timing and is an integer multiple of the frame sync frequency. The
internal master clock can be optionally derived from the PCLK source by setting the CMODE bit (bit 4, Command 46/47h) to one.
In this mode, the MCLK/E1 pin is free to be used as an E1 signal output. In GCI mode, since the master clock is derived only
from the DCL clock, this MCLK/E1 pin is always available as an E1 output. Clock mode options and E1 output functions are
shown in Figure 19.
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Zarlink Semiconductor Inc.
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