Le58083
Data Sheet
Figure 19. Clock Mode Options (PCM/MPI Mode)
MCLK/E1
PCLK
(= 0)
(= 1)
E1
Time
Slot
Assigner
(= 1)
(= 0)
CMODE
(= 1)
(= 0)
EE1
÷ N
DSP
Engine
CSEL
E1
Pulses
E1P
Notes:
1. CMODE = Command 46/47h
2. CSEL = Command 46/47h
3. EE1 = Command C8/C9h
4. E1P = Command C8/C9h
Bit 4
Bits 0–3
Bit 7
Bit 6
E1 Multiplex Operation
The Le58083 Octal SLAC device can multiplex input data from the CD1 SLIC device I/O pin into two separate status bits per
channel (CD1 and CD1B bits in the SLIC device Input/Output register, MPI Command 52/53h, GCI Command SOP 10 and CDA
and CDB bits in the Real Time Data register, MPI Command 4D/4Fh, GCI Command SOP 13, GCI C/I Channel) using the E1
multiplex mode. This multiplex mode provides the means to accommodate dual detect states when connected to an Zarlink
SLIC device, which also supports ground-key detection in addition to loop detect. Zarlink SLIC devices that support ground-key
detect use their E1 pin as an input to switch the SLIC device’s single detector (DET) output between internal loop detect or
ground-key detect comparators. Using the E1 multiplex mode, a single Le58083 Octal SLAC device can monitor both loop detect
and ground-key detect states of all eight connected SLIC devices without additional hardware. Although normally used for ground
key detect, this multiplex function can also be used for monitoring other signal states.
The E1 multiplex mode is selected by setting the EE1 bit (bit 7, MPI Command C8/C9h, GCI Command SOP 11) and CMODE
bit (bit 4, Command 46/47h) in the Le58083 Octal SLAC device. In PCM/MPI mode, the CMODE bit must be selected (CMODE
= 1) for the master clock to be derived from PCLK so that the MCLK/E1 pin can be used as an output for the E1 signal. The
multiplex mode is then turned on by setting the EE1 bit. With the E1 multiplex mode enabled, the Le58083 Octal SLAC device
generates the E1 output signal. This signal is a 31.25 µs (1/32 kHz) duration pulse occurring at a 4.923 kHz (64 kHz/13) rate. If
EE1 is reset,
MCLK/E1 is programmed as an input and should be connected to ground if it is not connected to a clock source. The polarity of
this E1 output is selected by the E1P bit (bit 6, MPI Command C8/C9h, GCI Command SOP 11) allowing this multiplex mode to
accommodate all SLIC devices regardless of their E1 high/low logic definition.
Figure 20 shows the SLIC device Input/Output register, I/O pins, E1 multiplex hardware operation for one Le58083 Octal SLAC
device channel. It also shows the operation of the Real Time Register. Each Le58083 Octal SLAC device E1 output signal
connects directly to the E1 inputs of all four connected SLIC devices and is used by those SLIC devices to select an internal
comparator to route to the SLIC device’s DET output. This E1 signal is also used internally by the Le58083 Octal SLAC device
for controlling the multiplex operation and timing.
The CD1 and CD1B bits of the SLIC device Input/Output register are isolated from the CD1 pin by transparent latches. When the
E1 pulse is off, the CD1 pin data is routed directly to the CD1 bit of the SLIC device I/O register and changes to the CD1B bit of
that register are disabled by its own latch. When E1 pulses on, the CD1 latch holds the last CD1 state in its register. At the same
32
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
