GP2021
20MHz
INTERNAL
CLOCK
MCLK
ARM_ALE
A<22:20>, A<9:0>
NROM
NEEPROM
D<15:0>
NRD
NOTE: NRW, NMREQ and DBE are assumed to be low
Figure 17 ROM (1 wait state) and EEPROM/spare (211 wait states) read cycles
20MHz
INTERNAL
CLOCK
MCLK
ARM_ALE
A<22:20>, A<9:0>
NEEPROM
NW<3:0>
DBE
D<15:0>
NOTE: NBW and NRW are assumed to be high for this cycle
Figure 18 EEPROM (or Spare) write cycle
20MHz
INTERNAL
CLOCK
MCLK
ARM_ALE
DBE
NRW
INTERNAL
WRITE
INTERNAL
READ
A<22:20>, A<9:0>
D<15:0>
VALID
VALID
VALID
NOTE: NBW is high and NMREQ low
Figure 19 Correlator write and read cycles
19