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XCS20-3PQ208C 参数 Datasheet PDF下载

XCS20-3PQ208C图片预览
型号: XCS20-3PQ208C
PDF下载: 下载PDF文件 查看货源
内容描述: 斯巴达和Spartan-XL系列现场可编程门阵列 [Spartan and Spartan-XL Families Field Programmable Gate Arrays]
分类和应用: 现场可编程门阵列
文件页数/大小: 82 页 / 848 K
品牌: XILINX [ XILINX, INC ]
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R
Spartan and Spartan-XL Families Field Programmable Gate Arrays  
Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
All timing parameters assume worst-case operating condi-  
tions (supply voltage and junction temperature). Values  
apply to all Spartan devices and are expressed in nanosec-  
onds unless otherwise noted.  
Speed Grade  
-4  
-3  
(1)  
Symbol  
Single Port RAM  
Size  
Min  
Max  
Min  
Max  
Units  
Write Operation  
T
Address write cycle time (clock K period)  
Clock K pulse width (active edge)  
Address setup time before clock K  
Address hold time after clock K  
DIN setup time before clock K  
DIN hold time after clock K  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
8.0  
8.0  
4.0  
4.0  
1.5  
1.5  
0.0  
0.0  
1.5  
1.5  
0.0  
0.0  
1.5  
1.5  
0.0  
0.0  
-
-
11.6  
11.6  
5.8  
5.8  
2.0  
2.0  
0.0  
0.0  
2.7  
1.7  
0.0  
0.0  
1.6  
1.6  
0.0  
0.0  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WCS  
T
-
-
WCTS  
T
-
-
WPS  
T
-
-
WPTS  
T
-
-
ASS  
T
-
-
ASTS  
T
-
-
AHS  
T
-
-
AHTS  
T
-
-
DSS  
T
-
-
DSTS  
T
-
-
DHS  
T
-
-
DHTS  
T
WE setup time before clock K  
WE hold time after clock K  
-
-
-
-
WSS  
T
T
T
WSTS  
T
-
-
WHS  
-
-
WHTS  
T
Data valid after clock K  
6.5  
7.0  
7.9  
9.3  
WOS  
-
-
WOTS  
Read Operation  
T
Address read cycle time  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
2.6  
3.8  
-
-
-
2.6  
3.8  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
RC  
T
RCT  
T
Data valid after address change (no Write  
Enable)  
1.2  
2.0  
-
1.6  
2.7  
-
ILO  
IHO  
T
-
-
T
Address setup time before clock K  
1.8  
2.9  
2.4  
3.9  
ICK  
T
-
-
IHCK  
Notes:  
1. Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.  
DS060 (v1.6) September 19, 2001  
Product Specification  
www.xilinx.com  
1-800-255-7778  
45  
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