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XCS20-3PQ208C 参数 Datasheet PDF下载

XCS20-3PQ208C图片预览
型号: XCS20-3PQ208C
PDF下载: 下载PDF文件 查看货源
内容描述: 斯巴达和Spartan-XL系列现场可编程门阵列 [Spartan and Spartan-XL Families Field Programmable Gate Arrays]
分类和应用: 现场可编程门阵列
文件页数/大小: 82 页 / 848 K
品牌: XILINX [ XILINX, INC ]
 浏览型号XCS20-3PQ208C的Datasheet PDF文件第40页浏览型号XCS20-3PQ208C的Datasheet PDF文件第41页浏览型号XCS20-3PQ208C的Datasheet PDF文件第42页浏览型号XCS20-3PQ208C的Datasheet PDF文件第43页浏览型号XCS20-3PQ208C的Datasheet PDF文件第45页浏览型号XCS20-3PQ208C的Datasheet PDF文件第46页浏览型号XCS20-3PQ208C的Datasheet PDF文件第47页浏览型号XCS20-3PQ208C的Datasheet PDF文件第48页  
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays  
Spartan CLB Switching Characteristic Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
All timing parameters assume worst-case operating condi-  
tions (supply voltage and junction temperature). Values  
apply to all Spartan devices and expressed in nanoseconds  
unless otherwise noted.  
Speed Grade  
-4  
-3  
Description  
Symbol  
Min  
Max  
Min  
Max  
Units  
Clocks  
T
Clock High time  
Clock Low time  
3.0  
3.0  
-
-
4.0  
4.0  
-
-
ns  
ns  
CH  
T
CL  
Combinatorial Delays  
T
F/G inputs to X/Y outputs  
-
-
-
1.2  
2.0  
1.7  
-
-
-
1.6  
2.7  
2.2  
ns  
ns  
ns  
ILO  
T
F/G inputs via H to X/Y outputs  
C inputs via H1 via H to X/Y outputs  
IHO  
T
HH1O  
CLB Fast Carry Logic  
Operand inputs (F1, F2, G1, G4) to C  
T
-
-
-
-
-
1.7  
2.8  
1.2  
2.0  
0.5  
-
-
-
-
-
2.1  
3.7  
1.4  
2.6  
0.6  
ns  
ns  
ns  
ns  
ns  
OPCY  
OUT  
T
Add/Subtract input (F3) to C  
OUT  
ASCY  
T
Initialization inputs (F1, F3) to C  
OUT  
INCY  
T
C
C
through function generators to X/Y outputs  
SUM  
IN  
T
to C  
, bypass function generators  
OUT  
BYP  
IN  
Sequential Delays  
Clock K to Flip-Flop outputs Q  
Setup Time before Clock K  
T
-
2.1  
-
2.8  
ns  
CKO  
T
F/G inputs  
1.8  
2.9  
2.3  
1.3  
2.0  
2.5  
-
-
-
-
-
-
2.4  
3.9  
3.3  
2.0  
2.6  
4.0  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ICK  
T
F/G inputs via H  
IHCK  
T
C inputs via H1 through H  
C inputs via DIN  
HH1CK  
T
DICK  
T
C inputs via EC  
ECCK  
T
C inputs via S/R, going Low (inactive)  
RCK  
Hold Time after Clock K  
All Hold times, all devices  
Set/Reset Direct  
0.0  
-
0.0  
-
ns  
T
Width (High)  
3.0  
-
-
4.0  
-
-
ns  
ns  
RPW  
T
Delay from C inputs via S/R, going High to Q  
3.0  
4.0  
RIO  
Global Set/Reset  
T
Minimum GSR pulse width  
11.5  
-
13.5  
-
ns  
MRW  
T
Delay from GSR input to any Q  
See page 50 for T  
values per device.  
RRI  
MRQ  
F
Toggle Frequency (MHz)  
-
166  
-
125  
MHz  
TOG  
(for export control purposes)  
44  
www.xilinx.com  
DS060 (v1.6) September 19, 2001  
1-800-255-7778  
Product Specification  
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