R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan DC Characteristics Over Operating Conditions
Symbol
Description
High-level output voltage @ I = –4.0 mA, V min
Min
Max
-
Units
V
V
TTL outputs
2.4
OH
OH
CC
High-level output voltage @ I = –1.0 mA, V min
CMOS outputs
TTL outputs
V – 0.5
CC
-
V
OH
CC
(1)
V
V
Low-level output voltage @ I = 12.0 mA, V min
-
0.4
0.4
-
V
OL
OL
CC
CMOS outputs
-
3.0
-
V
Data retention supply voltage (below which configuration data may be lost)
V
DR
(2)
I
Quiescent FPGA supply current
Commercial
Industrial
3.0
6.0
+10
10
0.25
-
mA
mA
µA
pF
mA
mA
CCO
-
I
Input or output leakage current
–10
-
L
C
Input capacitance (sample tested)
IN
I
Pad pull-up (when selected) @ V = 0V (sample tested)
0.02
0.02
RPU
RPD
IN
I
Pad pull-down (when selected) @ V = 5V (sample tested)
IN
Notes:
1. With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
2. With no output current loads, no active input pull-up resistors, all package pins at V or GND, and the FPGA configured with a Tie
CC
option.
Spartan Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by
the global clock net.
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
Speed Grade
-4
Max
2.0
2.4
2.8
3.2
3.5
2.5
2.9
3.3
3.6
3.9
-3
Max
4.0
4.3
5.4
5.8
6.4
4.4
4.7
5.8
6.2
6.7
Symbol
Description
Device
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
Units
ns
T
From pad through Primary buffer, to any clock K
PG
ns
ns
ns
ns
T
From pad through Secondary buffer, to any clock K
ns
SG
ns
ns
ns
ns
DS060 (v1.6) September 19, 2001
www.xilinx.com
43
Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
